jeanlemotan
157 lines
4.8 KiB
C
157 lines
4.8 KiB
C
/////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) Electronic Arts Inc. All rights reserved.
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/////////////////////////////////////////////////////////////////////////////////
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#ifndef EASTL_ATOMIC_INTERNAL_ARCH_ARM_LOAD_H
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#define EASTL_ATOMIC_INTERNAL_ARCH_ARM_LOAD_H
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#if defined(EA_PRAGMA_ONCE_SUPPORTED)
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#pragma once
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#endif
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/////////////////////////////////////////////////////////////////////////////////
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//
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// void EASTL_ARCH_ATOMIC_LOAD_*_N(type, type ret, type * ptr)
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//
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#if defined(EA_COMPILER_MSVC)
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/**
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* NOTE:
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*
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* Even 8-byte aligned 64-bit memory accesses on ARM32 are not
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* guaranteed to be atomic on all ARM32 cpus. Only guaranteed on
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* cpus with the LPAE extension. We need to use a
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* ldrexd instruction in order to ensure no shearing is observed
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* for all ARM32 processors.
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*/
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#if defined(EA_PROCESSOR_ARM32)
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#define EASTL_ARCH_ATOMIC_ARM32_LDREXD(ret, ptr) \
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ret = __ldrexd((ptr))
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#endif
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#define EASTL_ARCH_ATOMIC_ARM_LOAD_N(integralType, bits, type, ret, ptr) \
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{ \
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integralType retIntegral; \
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retIntegral = EA_PREPROCESSOR_JOIN(__iso_volatile_load, bits)(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(integralType, (ptr))); \
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\
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ret = EASTL_ATOMIC_TYPE_PUN_CAST(type, retIntegral); \
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}
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#define EASTL_ARCH_ATOMIC_ARM_LOAD_8(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_N(__int8, 8, type, ret, ptr)
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#define EASTL_ARCH_ATOMIC_ARM_LOAD_16(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_N(__int16, 16, type, ret, ptr)
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#define EASTL_ARCH_ATOMIC_ARM_LOAD_32(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_N(__int32, 32, type, ret, ptr)
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#if defined(EA_PROCESSOR_ARM32)
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#define EASTL_ARCH_ATOMIC_LOAD_64(type, ret, ptr) \
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{ \
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__int64 loadRet64; \
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EASTL_ARCH_ATOMIC_ARM32_LDREXD(loadRet64, EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(__int64, (ptr))); \
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\
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ret = EASTL_ATOMIC_TYPE_PUN_CAST(type, loadRet64); \
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}
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#else
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#define EASTL_ARCH_ATOMIC_ARM_LOAD_64(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_N(__int64, 64, type, ret, ptr)
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#endif
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/**
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* NOTE:
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*
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* The ARM documentation states the following:
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* A 64-bit pair requires the address to be quadword aligned and is single-copy atomic for each doubleword at doubleword granularity
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*
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* Thus we must ensure the store succeeds inorder for the load to be observed as atomic.
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* Thus we must use the full cmpxchg in order to do a proper atomic load.
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*/
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#define EASTL_ARCH_ATOMIC_ARM_LOAD_128(type, ret, ptr, MemoryOrder) \
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{ \
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bool cmpxchgRetBool; \
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ret = *(ptr); \
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do \
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{ \
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EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_CMPXCHG_STRONG_, MemoryOrder), _128)(type, cmpxchgRetBool, \
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ptr, &(ret), ret); \
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} while (!cmpxchgRetBool); \
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}
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#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_8(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_8(type, ret, ptr)
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#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_16(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_16(type, ret, ptr)
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#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_32(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_32(type, ret, ptr)
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#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_64(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_64(type, ret, ptr)
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#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_128(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_128(type, ret, ptr, RELAXED)
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#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_8(type, ret, ptr); \
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EASTL_ATOMIC_CPU_MB()
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#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_16(type, ret, ptr); \
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EASTL_ATOMIC_CPU_MB()
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#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_32(type, ret, ptr); \
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EASTL_ATOMIC_CPU_MB()
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#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_64(type, ret, ptr); \
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EASTL_ATOMIC_CPU_MB()
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#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_128(type, ret, ptr, ACQUIRE)
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#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_8(type, ret, ptr); \
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EASTL_ATOMIC_CPU_MB()
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#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_16(type, ret, ptr); \
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EASTL_ATOMIC_CPU_MB()
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#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_32(type, ret, ptr); \
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EASTL_ATOMIC_CPU_MB()
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#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_64(type, ret, ptr); \
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EASTL_ATOMIC_CPU_MB()
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#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128(type, ret, ptr) \
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EASTL_ARCH_ATOMIC_ARM_LOAD_128(type, ret, ptr, SEQ_CST)
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#endif
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#endif /* EASTL_ATOMIC_INTERNAL_ARCH_ARM_LOAD_H */
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