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This commit is contained in:
jeanlemotan
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/////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) Electronic Arts Inc. All rights reserved.
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/////////////////////////////////////////////////////////////////////////////////
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#ifndef EASTL_ATOMIC_INTERNAL_ARCH_H
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#define EASTL_ATOMIC_INTERNAL_ARCH_H
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#if defined(EA_PRAGMA_ONCE_SUPPORTED)
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#pragma once
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#endif
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/////////////////////////////////////////////////////////////////////////////////
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//
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// Include the architecture specific implementations
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//
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#if defined(EA_PROCESSOR_X86) || defined(EA_PROCESSOR_X86_64)
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#include "x86/arch_x86.h"
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#elif defined(EA_PROCESSOR_ARM32) || defined(EA_PROCESSOR_ARM64)
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#include "arm/arch_arm.h"
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#endif
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/////////////////////////////////////////////////////////////////////////////////
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#include "arch_fetch_add.h"
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#include "arch_fetch_sub.h"
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#include "arch_fetch_and.h"
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#include "arch_fetch_xor.h"
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#include "arch_fetch_or.h"
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#include "arch_add_fetch.h"
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#include "arch_sub_fetch.h"
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#include "arch_and_fetch.h"
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#include "arch_xor_fetch.h"
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#include "arch_or_fetch.h"
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#include "arch_exchange.h"
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#include "arch_cmpxchg_weak.h"
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#include "arch_cmpxchg_strong.h"
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#include "arch_load.h"
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#include "arch_store.h"
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#include "arch_compiler_barrier.h"
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#include "arch_cpu_pause.h"
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#include "arch_memory_barrier.h"
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#include "arch_signal_fence.h"
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#include "arch_thread_fence.h"
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#endif /* EASTL_ATOMIC_INTERNAL_ARCH_H */
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@@ -0,0 +1,173 @@
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/////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) Electronic Arts Inc. All rights reserved.
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/////////////////////////////////////////////////////////////////////////////////
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#ifndef EASTL_ATOMIC_INTERNAL_ARCH_ADD_FETCH_H
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#define EASTL_ATOMIC_INTERNAL_ARCH_ADD_FETCH_H
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#if defined(EA_PRAGMA_ONCE_SUPPORTED)
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#pragma once
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#endif
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/////////////////////////////////////////////////////////////////////////////////
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//
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// void EASTL_ARCH_ATOMIC_ADD_FETCH_*_N(type, type ret, type * ptr, type val)
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//
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_8)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_8)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_8)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_8)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_8)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_16)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_16)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_16)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_16)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_16)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_32)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_32_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_32_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_32)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_32_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_32_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_32)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_32_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_32_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_32)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_32_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_32_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_32)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_32_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_32_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_64)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_64_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_64_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_64)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_64_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_64_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_64)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_64_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_64_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_64)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_64_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_64_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_64)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_64_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_64_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_128)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_128_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_128_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_128)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_128_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_128_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_128)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_128_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_128_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_128)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_128_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_128_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_128)
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_128_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_128_AVAILABLE 0
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#endif
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#endif /* EASTL_ATOMIC_INTERNAL_ARCH_ADD_FETCH_H */
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@@ -0,0 +1,173 @@
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/////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) Electronic Arts Inc. All rights reserved.
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/////////////////////////////////////////////////////////////////////////////////
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#ifndef EASTL_ATOMIC_INTERNAL_ARCH_AND_FETCH_H
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#define EASTL_ATOMIC_INTERNAL_ARCH_AND_FETCH_H
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#if defined(EA_PRAGMA_ONCE_SUPPORTED)
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#pragma once
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#endif
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/////////////////////////////////////////////////////////////////////////////////
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//
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// void EASTL_ARCH_ATOMIC_AND_FETCH_*_N(type, type ret, type * ptr, type val)
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//
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_8)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_8)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_8)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_8)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_8)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_8_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_8_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_16)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_16)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_16)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_16)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_16)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_16_AVAILABLE 1
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#else
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#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_16_AVAILABLE 0
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#endif
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#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_32)
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#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_32_AVAILABLE 1
|
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#else
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||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_32_AVAILABLE 0
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||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_32)
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||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_AND_FETCH_H */
|
||||
@@ -0,0 +1,430 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_CMPXCHG_STRONG_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_CMPXCHG_STRONG_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_*_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_CMPXCHG_STRONG_H */
|
||||
@@ -0,0 +1,430 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_CMPXCHG_WEAK_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_CMPXCHG_WEAK_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_*_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_8_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_16_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_32_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_64_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_128_AVAILABLE \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128_AVAILABLE
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_CMPXCHG_WEAK_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_COMPILER_BARRIER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_COMPILER_BARRIER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_COMPILER_BARRIER_AVAILABLE 0
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY_AVAILABLE 0
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_COMPILER_BARRIER_H */
|
||||
@@ -0,0 +1,25 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// copyright (c) electronic arts inc. all rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_CPU_PAUSE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_CPU_PAUSE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_PAUSE()
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_CPU_PAUSE)
|
||||
#define EASTL_ARCH_ATOMIC_CPU_PAUSE_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CPU_PAUSE_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_CPU_PAUSE_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_EXCHANGE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_EXCHANGE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_EXCHANGE_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_EXCHANGE_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_FETCH_ADD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_FETCH_ADD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_ADD_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_FETCH_ADD_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_FETCH_AND_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_FETCH_AND_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_AND_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_FETCH_AND_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_FETCH_OR_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_FETCH_OR_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_OR_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_FETCH_OR_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_FETCH_SUB_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_FETCH_SUB_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_SUB_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_FETCH_SUB_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_FETCH_XOR_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_FETCH_XOR_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_XOR_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_FETCH_XOR_H */
|
||||
@@ -0,0 +1,125 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_LOAD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_LOAD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_LOAD_*_N(type, type ret, type * ptr)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_32)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_64)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_READ_DEPENDS_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_LOAD_H */
|
||||
@@ -0,0 +1,47 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_MEMORY_BARRIER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_MEMORY_BARRIER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_MB()
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_CPU_MB)
|
||||
#define EASTL_ARCH_ATOMIC_CPU_MB_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CPU_MB_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_WMB()
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_CPU_WMB)
|
||||
#define EASTL_ARCH_ATOMIC_CPU_WMB_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CPU_WMB_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_RMB()
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_CPU_RMB)
|
||||
#define EASTL_ARCH_ATOMIC_CPU_RMB_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_CPU_RMB_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_MEMORY_BARRIER_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_OR_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_OR_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_OR_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_OR_FETCH_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_SIGNAL_FENCE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_SIGNAL_FENCE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SIGNAL_FENCE_RELAXED_AVAILABLE 0
|
||||
#define EASTL_ARCH_ATOMIC_SIGNAL_FENCE_ACQUIRE_AVAILABLE 0
|
||||
#define EASTL_ARCH_ATOMIC_SIGNAL_FENCE_RELEASE_AVAILABLE 0
|
||||
#define EASTL_ARCH_ATOMIC_SIGNAL_FENCE_ACQ_REL_AVAILABLE 0
|
||||
#define EASTL_ARCH_ATOMIC_SIGNAL_FENCE_SEQ_CST_AVAILABLE 0
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_SIGNAL_FENCE_H */
|
||||
@@ -0,0 +1,113 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_STORE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_STORE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_STORE_*_N(type, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_STORE_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_STORE_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_SUB_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_SUB_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_SUB_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_SUB_FETCH_H */
|
||||
@@ -0,0 +1,49 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_THREAD_FENCE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_THREAD_FENCE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_THREAD_FENCE_*()
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_THREAD_FENCE_RELAXED)
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_RELAXED_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_RELAXED_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQUIRE)
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQUIRE_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQUIRE_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_THREAD_FENCE_RELEASE)
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_RELEASE_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_RELEASE_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQ_REL)
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQ_REL_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQ_REL_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_THREAD_FENCE_SEQ_CST)
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_SEQ_CST_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_SEQ_CST_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_THREAD_FENCE_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_XOR_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_XOR_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_XOR_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_8)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_8)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_8)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_8)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_8)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_16)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_16)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_16)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_16)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_16)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_32)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_32)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_32)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_32)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_32)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_64)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_64)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_64)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_64)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_64)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_128)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_128)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_128)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_128)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_128)
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_XOR_FETCH_H */
|
||||
@@ -0,0 +1,89 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_ARM_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_ARM_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* NOTE: We use this mapping
|
||||
*
|
||||
* ARMv7 Mapping 'trailing sync;':
|
||||
*
|
||||
* Load Relaxed : ldr
|
||||
* Load Acquire : ldr; dmb ish
|
||||
* Load Seq_Cst : ldr; dmb ish
|
||||
*
|
||||
* Store Relaxed : str
|
||||
* Store Release : dmb ish; str
|
||||
* Store Seq_Cst : dmb ish; str; dmb ish
|
||||
*
|
||||
* Relaxed Fence :
|
||||
* Acquire Fence : dmb ish
|
||||
* Release Fence : dmb ish
|
||||
* Acq_Rel Fence : dmb ish
|
||||
* Seq_Cst Fence : dmb ish
|
||||
*/
|
||||
|
||||
/**
|
||||
* ARMv7 Mapping 'leading sync;';
|
||||
*
|
||||
* Load Relaxed : ldr
|
||||
* Load Acquire : ldr; dmb ish
|
||||
* Load Seq_Cst : dmb ish; ldr; dmb ish
|
||||
*
|
||||
* Store Relaxed : str
|
||||
* Store Release : dmb ish; str
|
||||
* Store Seq_Cst : dmb ish: str
|
||||
*
|
||||
* Relaxed Fence :
|
||||
* Acquire Fence : dmb ish
|
||||
* Release Fence : dmb ish
|
||||
* Acq_Rel Fence : dmb ish
|
||||
* Seq_Cst Fence : dmb ish
|
||||
*/
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* On ARM32/64, we use the 'trailing sync;' convention with the stricter load acquire that uses
|
||||
* a dmb instead of a control dependency + isb to ensure the IRIW litmus test is satisfied
|
||||
* as one reason. See EASTL/atomic.h for futher explanation and deep-dive.
|
||||
*
|
||||
* For ARMv8 we could move to use the new proper store release and load acquire, RCsc variant.
|
||||
* All ARMv7 approaches work on ARMv8 and this code path is only used on msvc which isn't used
|
||||
* heavily. Most of the ARM code will end up going thru clang or gcc since microsoft arm devices
|
||||
* aren't that abundant.
|
||||
*/
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#if defined(EA_COMPILER_MSVC)
|
||||
|
||||
#if EA_PLATFORM_PTR_SIZE == 8
|
||||
#define EASTL_ARCH_ATOMIC_HAS_128BIT
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#include "arch_arm_load.h"
|
||||
#include "arch_arm_store.h"
|
||||
|
||||
#include "arch_arm_memory_barrier.h"
|
||||
|
||||
#include "arch_arm_thread_fence.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_ARM_H */
|
||||
@@ -0,0 +1,156 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_ARM_LOAD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_ARM_LOAD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_LOAD_*_N(type, type ret, type * ptr)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC)
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* Even 8-byte aligned 64-bit memory accesses on ARM32 are not
|
||||
* guaranteed to be atomic on all ARM32 cpus. Only guaranteed on
|
||||
* cpus with the LPAE extension. We need to use a
|
||||
* ldrexd instruction in order to ensure no shearing is observed
|
||||
* for all ARM32 processors.
|
||||
*/
|
||||
#if defined(EA_PROCESSOR_ARM32)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM32_LDREXD(ret, ptr) \
|
||||
ret = __ldrexd((ptr))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_LOAD_N(integralType, bits, type, ret, ptr) \
|
||||
{ \
|
||||
integralType retIntegral; \
|
||||
retIntegral = EA_PREPROCESSOR_JOIN(__iso_volatile_load, bits)(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(integralType, (ptr))); \
|
||||
\
|
||||
ret = EASTL_ATOMIC_TYPE_PUN_CAST(type, retIntegral); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_LOAD_8(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_N(__int8, 8, type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_LOAD_16(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_N(__int16, 16, type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_LOAD_32(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_N(__int32, 32, type, ret, ptr)
|
||||
|
||||
|
||||
#if defined(EA_PROCESSOR_ARM32)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_64(type, ret, ptr) \
|
||||
{ \
|
||||
__int64 loadRet64; \
|
||||
EASTL_ARCH_ATOMIC_ARM32_LDREXD(loadRet64, EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(__int64, (ptr))); \
|
||||
\
|
||||
ret = EASTL_ATOMIC_TYPE_PUN_CAST(type, loadRet64); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_LOAD_64(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_N(__int64, 64, type, ret, ptr)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* The ARM documentation states the following:
|
||||
* A 64-bit pair requires the address to be quadword aligned and is single-copy atomic for each doubleword at doubleword granularity
|
||||
*
|
||||
* Thus we must ensure the store succeeds inorder for the load to be observed as atomic.
|
||||
* Thus we must use the full cmpxchg in order to do a proper atomic load.
|
||||
*/
|
||||
#define EASTL_ARCH_ATOMIC_ARM_LOAD_128(type, ret, ptr, MemoryOrder) \
|
||||
{ \
|
||||
bool cmpxchgRetBool; \
|
||||
ret = *(ptr); \
|
||||
do \
|
||||
{ \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_CMPXCHG_STRONG_, MemoryOrder), _128)(type, cmpxchgRetBool, \
|
||||
ptr, &(ret), ret); \
|
||||
} while (!cmpxchgRetBool); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_8(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_8(type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_16(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_16(type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_32(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_32(type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_64(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_64(type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_128(type, ret, ptr, RELAXED)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_8(type, ret, ptr); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_16(type, ret, ptr); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_32(type, ret, ptr); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_64(type, ret, ptr); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_128(type, ret, ptr, ACQUIRE)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_8(type, ret, ptr); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_16(type, ret, ptr); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_32(type, ret, ptr); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_64(type, ret, ptr); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_ARM_LOAD_128(type, ret, ptr, SEQ_CST)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_ARM_LOAD_H */
|
||||
@@ -0,0 +1,97 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_ARM_MEMORY_BARRIER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_ARM_MEMORY_BARRIER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EA_COMPILER_MSVC) && !defined(EA_COMPILER_CLANG_CL)
|
||||
|
||||
#if defined(EA_PROCESSOR_ARM32)
|
||||
|
||||
#define EASTL_ARM_DMB_ISH _ARM_BARRIER_ISH
|
||||
|
||||
#define EASTL_ARM_DMB_ISHST _ARM_BARRIER_ISHST
|
||||
|
||||
#define EASTL_ARM_DMB_ISHLD _ARM_BARRIER_ISH
|
||||
|
||||
#elif defined(EA_PROCESSOR_ARM64)
|
||||
|
||||
#define EASTL_ARM_DMB_ISH _ARM64_BARRIER_ISH
|
||||
|
||||
#define EASTL_ARM_DMB_ISHST _ARM64_BARRIER_ISHST
|
||||
|
||||
#define EASTL_ARM_DMB_ISHLD _ARM64_BARRIER_ISHLD
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* While it makes no sense for a hardware memory barrier to not imply a compiler barrier.
|
||||
* MSVC docs do not explicitly state that, so better to be safe than sorry chasing down
|
||||
* hard to find bugs due to the compiler deciding to reorder things.
|
||||
*/
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_EMIT_DMB(option) \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER(); \
|
||||
__dmb(option); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
|
||||
#elif defined(EA_COMPILER_GNUC) || defined(__clang__)
|
||||
|
||||
#define EASTL_ARM_DMB_ISH ish
|
||||
|
||||
#define EASTL_ARM_DMB_ISHST ishst
|
||||
|
||||
#if defined(EA_PROCESSOR_ARM32)
|
||||
|
||||
#define EASTL_ARM_DMB_ISHLD ish
|
||||
|
||||
#elif defined(EA_PROCESSOR_ARM64)
|
||||
|
||||
#define EASTL_ARM_DMB_ISHLD ishld
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_EMIT_DMB(option) \
|
||||
__asm__ __volatile__ ("dmb " EA_STRINGIFY(option) ::: "memory")
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_MB()
|
||||
//
|
||||
#define EASTL_ARCH_ATOMIC_CPU_MB() \
|
||||
EASTL_ARCH_ATOMIC_ARM_EMIT_DMB(EASTL_ARM_DMB_ISH)
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_WMB()
|
||||
//
|
||||
#define EASTL_ARCH_ATOMIC_CPU_WMB() \
|
||||
EASTL_ARCH_ATOMIC_ARM_EMIT_DMB(EASTL_ARM_DMB_ISHST)
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_RMB()
|
||||
//
|
||||
#define EASTL_ARCH_ATOMIC_CPU_RMB() \
|
||||
EASTL_ARCH_ATOMIC_ARM_EMIT_DMB(EASTL_ARM_DMB_ISHLD)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_ARM_MEMORY_BARRIER_H */
|
||||
@@ -0,0 +1,142 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_ARM_STORE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_ARM_STORE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_STORE_*_N(type, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_STORE_N(integralType, bits, type, ptr, val) \
|
||||
EA_PREPROCESSOR_JOIN(__iso_volatile_store, bits)(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(integralType, (ptr)), EASTL_ATOMIC_TYPE_PUN_CAST(integralType, (val)))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_STORE_8(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_N(__int8, 8, type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_STORE_16(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_N(__int16, 16, type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_STORE_32(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_N(__int32, 32, type, ptr, val)
|
||||
|
||||
|
||||
#if defined(EA_PROCESSOR_ARM64)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_STORE_64(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_N(__int64, 64, type, ptr, val)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ARM_STORE_128(type, ptr, val, MemoryOrder) \
|
||||
{ \
|
||||
type exchange128; EA_UNUSED(exchange128); \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_EXCHANGE_, MemoryOrder), _128)(type, exchange128, ptr, val); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_8(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_8(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_16(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_16(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_32(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_32(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_128(type, ptr, val, RELAXED)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_8(type, ptr, val) \
|
||||
EASTL_ATOMIC_CPU_MB(); \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_8(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_16(type, ptr, val) \
|
||||
EASTL_ATOMIC_CPU_MB(); \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_16(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_32(type, ptr, val) \
|
||||
EASTL_ATOMIC_CPU_MB(); \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_32(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_128(type, ptr, val, RELEASE)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_8(type, ptr, val) \
|
||||
EASTL_ATOMIC_CPU_MB(); \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_8(type, ptr, val) ; \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_16(type, ptr, val) \
|
||||
EASTL_ATOMIC_CPU_MB(); \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_16(type, ptr, val); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_32(type, ptr, val) \
|
||||
EASTL_ATOMIC_CPU_MB(); \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_32(type, ptr, val); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_128(type, ptr, val, SEQ_CST)
|
||||
|
||||
|
||||
#if defined(EA_PROCESSOR_ARM32)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_64(type, ptr, val) \
|
||||
{ \
|
||||
type retExchange64; EA_UNUSED(retExchange64); \
|
||||
EASTL_ATOMIC_EXCHANGE_RELAXED_64(type, retExchange64, ptr, val); \
|
||||
}
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_64(type, ptr, val) \
|
||||
{ \
|
||||
type retExchange64; EA_UNUSED(retExchange64); \
|
||||
EASTL_ATOMIC_EXCHANGE_RELEASE_64(type, retExchange64, ptr, val); \
|
||||
}
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64(type, ptr, val) \
|
||||
{ \
|
||||
type retExchange64; EA_UNUSED(retExchange64); \
|
||||
EASTL_ATOMIC_EXCHANGE_SEQ_CST_64(type, retExchange64, ptr, val); \
|
||||
}
|
||||
|
||||
|
||||
#elif defined(EA_PROCESSOR_ARM64)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_64(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_64(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_64(type, ptr, val) \
|
||||
EASTL_ATOMIC_CPU_MB(); \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_64(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64(type, ptr, val) \
|
||||
EASTL_ATOMIC_CPU_MB(); \
|
||||
EASTL_ARCH_ATOMIC_ARM_STORE_64(type, ptr, val); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_ARM_STORE_H */
|
||||
@@ -0,0 +1,37 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_ARM_THREAD_FENCE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_ARM_THREAD_FENCE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_THREAD_FENCE_*()
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_RELAXED()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQUIRE() \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_RELEASE() \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQ_REL() \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_SEQ_CST() \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_ARM_THREAD_FENCE_H */
|
||||
@@ -0,0 +1,158 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* x86 && x64 Mappings
|
||||
*
|
||||
* Load Relaxed : MOV
|
||||
* Load Acquire : MOV; COMPILER_BARRIER;
|
||||
* Load Seq_Cst : MOV; COMPILER_BARRIER;
|
||||
*
|
||||
* Store Relaxed : MOV
|
||||
* Store Release : COMPILER_BARRIER; MOV;
|
||||
* Store Seq_Cst : LOCK XCHG : MOV; MFENCE;
|
||||
*
|
||||
* Relaxed Fence :
|
||||
* Acquire Fence : COMPILER_BARRIER
|
||||
* Release Fence : COMPILER_BARRIER
|
||||
* Acq_Rel Fence : COMPILER_BARRIER
|
||||
* Seq_Cst FENCE : MFENCE
|
||||
*/
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#if (defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64)
|
||||
#define EASTL_ARCH_ATOMIC_HAS_128BIT
|
||||
#elif defined(EA_COMPILER_MSVC)
|
||||
#if EA_PLATFORM_PTR_SIZE == 8
|
||||
#define EASTL_ARCH_ATOMIC_HAS_128BIT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* On 32-bit x86 CPUs Intel Pentium and newer, AMD K5 and newer
|
||||
* and any i586 class of x86 CPUs support only 64-bit cmpxchg
|
||||
* known as cmpxchg8b.
|
||||
*
|
||||
* On these class of cpus we can guarantee that 64-bit loads/stores are
|
||||
* also atomic by using the SSE2 movq, SSE1 movlps, or x87 fild/fstp instructions.
|
||||
*
|
||||
* We support all other atomic operations
|
||||
* on compilers that only provide this 64-bit cmpxchg instruction
|
||||
* by wrapping them around the 64-bit cmpxchg8b instruction.
|
||||
*/
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_NOP_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
static_assert(false, "EASTL_ARCH_ATOMIC_X86_NOP_PRE_COMPUTE_DESIRED() must be implmented!");
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET(ret, prevObserved, val)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, MemoryOrder, PRE_COMPUTE_DESIRED, POST_COMPUTE_RET) \
|
||||
{ \
|
||||
EASTL_ATOMIC_DEFAULT_INIT(bool, cmpxchgRet); \
|
||||
EASTL_ATOMIC_LOAD_RELAXED_64(type, ret, ptr); \
|
||||
do \
|
||||
{ \
|
||||
type computedDesired; \
|
||||
PRE_COMPUTE_DESIRED(computedDesired, ret, (val)); \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_CMPXCHG_STRONG_, MemoryOrder), _64)(type, cmpxchgRet, ptr, &(ret), computedDesired); \
|
||||
} while (!cmpxchgRet); \
|
||||
POST_COMPUTE_RET(ret, ret, (val)); \
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* 64-bit x64 CPUs support only 128-bit cmpxchg known as cmpxchg16b.
|
||||
*
|
||||
* We support all other atomic operations by wrapping them around
|
||||
* the 128-bit cmpxchg16b instruction.
|
||||
*
|
||||
* 128-bit loads are only atomic by using the cmpxchg16b instruction.
|
||||
* SSE 128-bit loads are not guaranteed to be atomic even though some CPUs
|
||||
* make them atomic such as AMD Ryzen or Intel SandyBridge.
|
||||
*/
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_NOP_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
static_assert(false, "EASTL_ARCH_ATOMIC_X86_NOP_PRE_COMPUTE_DESIRED() must be implmented!");
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET(ret, prevObserved, val)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, MemoryOrder, PRE_COMPUTE_DESIRED, POST_COMPUTE_RET) \
|
||||
{ \
|
||||
EASTL_ATOMIC_DEFAULT_INIT(bool, cmpxchgRet); \
|
||||
/* This is intentionally a non-atomic 128-bit load which may observe shearing. */ \
|
||||
/* Either we do not observe *(ptr) but then the cmpxchg will fail and the observed */ \
|
||||
/* atomic load will be returned. Or the non-atomic load got lucky and the cmpxchg succeeds */ \
|
||||
/* because the observed value equals the value in *(ptr) thus we optimistically do a non-atomic load. */ \
|
||||
ret = *(ptr); \
|
||||
do \
|
||||
{ \
|
||||
type computedDesired; \
|
||||
PRE_COMPUTE_DESIRED(computedDesired, ret, (val)); \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_CMPXCHG_STRONG_, MemoryOrder), _128)(type, cmpxchgRet, ptr, &(ret), computedDesired); \
|
||||
} while (!cmpxchgRet); \
|
||||
POST_COMPUTE_RET(ret, ret, (val)); \
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#include "arch_x86_fetch_add.h"
|
||||
#include "arch_x86_fetch_sub.h"
|
||||
|
||||
#include "arch_x86_fetch_and.h"
|
||||
#include "arch_x86_fetch_xor.h"
|
||||
#include "arch_x86_fetch_or.h"
|
||||
|
||||
#include "arch_x86_add_fetch.h"
|
||||
#include "arch_x86_sub_fetch.h"
|
||||
|
||||
#include "arch_x86_and_fetch.h"
|
||||
#include "arch_x86_xor_fetch.h"
|
||||
#include "arch_x86_or_fetch.h"
|
||||
|
||||
#include "arch_x86_exchange.h"
|
||||
|
||||
#include "arch_x86_cmpxchg_weak.h"
|
||||
#include "arch_x86_cmpxchg_strong.h"
|
||||
|
||||
#include "arch_x86_memory_barrier.h"
|
||||
|
||||
#include "arch_x86_thread_fence.h"
|
||||
|
||||
#include "arch_x86_load.h"
|
||||
#include "arch_x86_store.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_H */
|
||||
@@ -0,0 +1,96 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_ADD_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_ADD_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_ADD_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) + (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) + (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) + (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) + (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_ADD_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_ADD_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_ADD_FETCH_H */
|
||||
@@ -0,0 +1,96 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_AND_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_AND_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_AND_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) & (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) & (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) & (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) & (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_AND_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_AND_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_AND_FETCH_H */
|
||||
@@ -0,0 +1,69 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_CMPXCHG_STRONG_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_CMPXCHG_STRONG_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_*_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired) \
|
||||
{ \
|
||||
/* Compare RDX:RAX with m128. If equal, set ZF and load RCX:RBX into m128. Else, clear ZF and load m128 into RDX:RAX. */ \
|
||||
__asm__ __volatile__ ("lock; cmpxchg16b %2\n" /* cmpxchg16b sets/clears ZF */ \
|
||||
"sete %3" /* If ZF == 1, set the return value to 1 */ \
|
||||
/* Output Operands */ \
|
||||
: "=a"((EASTL_ATOMIC_TYPE_CAST(uint64_t, (expected)))[0]), "=d"((EASTL_ATOMIC_TYPE_CAST(uint64_t, (expected)))[1]), \
|
||||
"+m"(*(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(__uint128_t, (ptr)))), \
|
||||
"=rm"((ret)) \
|
||||
/* Input Operands */ \
|
||||
: "b"((EASTL_ATOMIC_TYPE_CAST(uint64_t, &(desired)))[0]), "c"((EASTL_ATOMIC_TYPE_CAST(uint64_t, &(desired)))[1]), \
|
||||
"a"((EASTL_ATOMIC_TYPE_CAST(uint64_t, (expected)))[0]), "d"((EASTL_ATOMIC_TYPE_CAST(uint64_t, (expected)))[1]) \
|
||||
/* Clobbers */ \
|
||||
: "memory", "cc"); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ARCH_ATOMIC_X86_CMPXCHG_STRONG_128_IMPL(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_CMPXCHG_STRONG_H */
|
||||
@@ -0,0 +1,52 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_CMPXCHG_WEAK_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_CMPXCHG_WEAK_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_*_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_CMPXCHG_WEAK_H */
|
||||
@@ -0,0 +1,91 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_EXCHANGE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_EXCHANGE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_EXCHANGE_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_EXCHANGE_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = (val)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_EXCHANGE_128(type, ret, ptr, val, MemoryOrder) \
|
||||
{ \
|
||||
EASTL_ATOMIC_DEFAULT_INIT(bool, cmpxchgRet); \
|
||||
/* This is intentionally a non-atomic 128-bit load which may observe shearing. */ \
|
||||
/* Either we do not observe *(ptr) but then the cmpxchg will fail and the observed */ \
|
||||
/* atomic load will be returned. Or the non-atomic load got lucky and the cmpxchg succeeds */ \
|
||||
/* because the observed value equals the value in *(ptr) thus we optimistically do a non-atomic load. */ \
|
||||
ret = *(ptr); \
|
||||
do \
|
||||
{ \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_CMPXCHG_STRONG_, MemoryOrder), _128)(type, cmpxchgRet, ptr, &(ret), val); \
|
||||
} while (!cmpxchgRet); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_128(type, ret, ptr, val, RELAXED)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_128(type, ret, ptr, val, ACQUIRE)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_128(type, ret, ptr, val, RELEASE)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_128(type, ret, ptr, val, ACQ_REL)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_EXCHANGE_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_EXCHANGE_128(type, ret, ptr, val, SEQ_CST)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_EXCHANGE_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_ADD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_ADD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_ADD_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) + (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) + (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_ADD_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_ADD_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_ADD_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_AND_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_AND_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_AND_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) & (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) & (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_AND_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_AND_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_AND_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_OR_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_OR_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_OR_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) | (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) | (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_OR_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_OR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_OR_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_SUB_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_SUB_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_SUB_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) - (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) - (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_SUB_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_SUB_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_SUB_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_XOR_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_XOR_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_FETCH_XOR_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) ^ (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) ^ (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_FETCH_XOR_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_FETCH_XOR_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_NOP_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_FETCH_XOR_H */
|
||||
@@ -0,0 +1,164 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_LOAD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_LOAD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_LOAD_*_N(type, type ret, type * ptr)
|
||||
//
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* Since the cmpxchg 128-bit inline assembly does a sete in the asm to set the return boolean,
|
||||
* it doesn't get dead-store removed even though we don't care about the success of the
|
||||
* cmpxchg since the compiler cannot reason about what is inside asm blocks.
|
||||
* Thus this variant just does the minimum required to do an atomic load.
|
||||
*/
|
||||
#define EASTL_ARCH_ATOMIC_X86_LOAD_128(type, ret, ptr, MemoryOrder) \
|
||||
{ \
|
||||
EASTL_ATOMIC_FIXED_WIDTH_TYPE_128 expected = 0; \
|
||||
ret = EASTL_ATOMIC_TYPE_PUN_CAST(type, expected); \
|
||||
\
|
||||
/* Compare RDX:RAX with m128. If equal, set ZF and load RCX:RBX into m128. Else, clear ZF and load m128 into RDX:RAX. */ \
|
||||
__asm__ __volatile__ ("lock; cmpxchg16b %2" /* cmpxchg16b sets/clears ZF */ \
|
||||
/* Output Operands */ \
|
||||
: "=a"((EASTL_ATOMIC_TYPE_CAST(uint64_t, &(ret)))[0]), "=d"((EASTL_ATOMIC_TYPE_CAST(uint64_t, &(ret)))[1]), \
|
||||
"+m"(*(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(__uint128_t, (ptr)))) \
|
||||
/* Input Operands */ \
|
||||
: "b"((EASTL_ATOMIC_TYPE_CAST(uint64_t, &(ret)))[0]), "c"((EASTL_ATOMIC_TYPE_CAST(uint64_t, &(ret)))[1]), \
|
||||
"a"((EASTL_ATOMIC_TYPE_CAST(uint64_t, &(ret)))[0]), "d"((EASTL_ATOMIC_TYPE_CAST(uint64_t, &(ret)))[1]) \
|
||||
/* Clobbers */ \
|
||||
: "memory", "cc"); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_128(type, ret, ptr, RELAXED)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_128(type, ret, ptr, ACQUIRE)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_128(type, ret, ptr, SEQ_CST)
|
||||
|
||||
#elif defined(EA_COMPILER_MSVC)
|
||||
|
||||
|
||||
#if defined(EA_COMPILER_MSVC) && (EA_COMPILER_VERSION >= 1920) // >= VS2019
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_LOAD_N(integralType, bits, type, ret, ptr) \
|
||||
{ \
|
||||
integralType retIntegral; \
|
||||
retIntegral = EA_PREPROCESSOR_JOIN(__iso_volatile_load, bits)(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(integralType, (ptr))); \
|
||||
\
|
||||
ret = EASTL_ATOMIC_TYPE_PUN_CAST(type, retIntegral); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_LOAD_N(integralType, bits, type, ret, ptr) \
|
||||
{ \
|
||||
integralType retIntegral; \
|
||||
retIntegral = (*(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(integralType, (ptr)))); \
|
||||
\
|
||||
ret = EASTL_ATOMIC_TYPE_PUN_CAST(type, retIntegral); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_LOAD_128(type, ret, ptr, MemoryOrder) \
|
||||
{ \
|
||||
EASTL_ATOMIC_FIXED_WIDTH_TYPE_128 expected{0, 0}; \
|
||||
ret = EASTL_ATOMIC_TYPE_PUN_CAST(type, expected); \
|
||||
\
|
||||
bool cmpxchgRetBool; EA_UNUSED(cmpxchgRetBool); \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_CMPXCHG_STRONG_, MemoryOrder), _128)(type, cmpxchgRetBool, ptr, &(ret), ret); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_LOAD_8(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_N(__int8, 8, type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_LOAD_16(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_N(__int16, 16, type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_LOAD_32(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_N(__int32, 32, type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_LOAD_64(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_N(__int64, 64, type, ret, ptr)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_8(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_8(type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_16(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_16(type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_32(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_32(type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_64(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_64(type, ret, ptr)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_RELAXED_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_128(type, ret, ptr, RELAXED)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_8(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_8(type, ret, ptr); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_16(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_16(type, ret, ptr); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_32(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_32(type, ret, ptr); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_64(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_64(type, ret, ptr); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_ACQUIRE_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_128(type, ret, ptr, ACQUIRE)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_8(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_8(type, ret, ptr); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_16(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_16(type, ret, ptr); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_32(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_32(type, ret, ptr); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_64(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_64(type, ret, ptr); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_LOAD_SEQ_CST_128(type, ret, ptr) \
|
||||
EASTL_ARCH_ATOMIC_X86_LOAD_128(type, ret, ptr, SEQ_CST)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_LOAD_H */
|
||||
@@ -0,0 +1,104 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_MEMORY_BARRIER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_MEMORY_BARRIER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_MB()
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC)
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
* While it makes no sense for a hardware memory barrier to not imply a compiler barrier.
|
||||
* MSVC docs do not explicitly state that, so better to be safe than sorry chasing down
|
||||
* hard to find bugs due to the compiler deciding to reorder things.
|
||||
*/
|
||||
|
||||
#if 1
|
||||
|
||||
// 4459 : declaration of 'identifier' hides global declaration
|
||||
// 4456 : declaration of 'identifier' hides previous local declaration
|
||||
#define EASTL_ARCH_ATOMIC_CPU_MB() \
|
||||
{ \
|
||||
EA_DISABLE_VC_WARNING(4459 4456); \
|
||||
volatile long _; \
|
||||
_InterlockedExchangeAdd(&_, 0); \
|
||||
EA_RESTORE_VC_WARNING(); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CPU_MB() \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER(); \
|
||||
_mm_mfence(); \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#endif
|
||||
|
||||
#elif defined(__clang__) || defined(EA_COMPILER_GNUC)
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* mfence orders all loads/stores to/from all memory types.
|
||||
* We only care about ordinary cacheable memory so lighter weight locked instruction
|
||||
* is far faster than a mfence to get a full memory barrier.
|
||||
* lock; addl against the top of the stack is good because:
|
||||
* distinct for every thread so prevents false sharing
|
||||
* that cacheline is most likely cache hot
|
||||
*
|
||||
* We intentionally do it below the stack pointer to avoid false RAW register dependencies,
|
||||
* in cases where the compiler reads from the stack pointer after the lock; addl instruction
|
||||
*
|
||||
* Accounting for Red Zones or Cachelines doesn't provide extra benefit.
|
||||
*/
|
||||
|
||||
#if defined(EA_PROCESSOR_X86)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CPU_MB() \
|
||||
__asm__ __volatile__ ("lock; addl $0, -4(%%esp)" ::: "memory", "cc")
|
||||
|
||||
#elif defined(EA_PROCESSOR_X86_64)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CPU_MB() \
|
||||
__asm__ __volatile__ ("lock; addl $0, -8(%%rsp)" ::: "memory", "cc")
|
||||
|
||||
#else
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_CPU_MB() \
|
||||
__asm__ __volatile__ ("mfence" ::: "memory")
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_WMB()
|
||||
//
|
||||
#define EASTL_ARCH_ATOMIC_CPU_WMB() \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_CPU_RMB()
|
||||
//
|
||||
#define EASTL_ARCH_ATOMIC_CPU_RMB() \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_MEMORY_BARRIER_H */
|
||||
@@ -0,0 +1,96 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_OR_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_OR_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_OR_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) | (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) | (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) | (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) | (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_OR_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_OR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_OR_FETCH_H */
|
||||
@@ -0,0 +1,171 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_STORE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_STORE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_STORE_*_N(type, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC)
|
||||
|
||||
|
||||
#if defined(EA_COMPILER_MSVC) && (EA_COMPILER_VERSION >= 1920) // >= VS2019
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_STORE_N(integralType, bits, type, ptr, val) \
|
||||
EA_PREPROCESSOR_JOIN(__iso_volatile_store, bits)(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(integralType, (ptr)), EASTL_ATOMIC_TYPE_PUN_CAST(integralType, (val)))
|
||||
|
||||
#else
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_STORE_N(integralType, bits, type, ptr, val) \
|
||||
{ \
|
||||
integralType valIntegral = EASTL_ATOMIC_TYPE_PUN_CAST(integralType, (val)); \
|
||||
\
|
||||
(*(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(integralType, (ptr)))) = valIntegral; \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_STORE_128(type, ptr, val, MemoryOrder) \
|
||||
{ \
|
||||
type exchange128; EA_UNUSED(exchange128); \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_EXCHANGE_, MemoryOrder), _128)(type, exchange128, ptr, val); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_STORE_8(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_N(__int8, 8, type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_STORE_16(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_N(__int16, 16, type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_STORE_32(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_N(__int32, 32, type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_STORE_64(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_N(__int64, 64, type, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_8(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_8(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_16(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_16(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_32(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_32(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_64(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_64(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_128(type, ptr, val, RELAXED)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_8(type, ptr, val) \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER(); \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_8(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_16(type, ptr, val) \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER(); \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_16(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_32(type, ptr, val) \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER(); \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_32(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_64(type, ptr, val) \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER(); \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_64(type, ptr, val)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_128(type, ptr, val, RELEASE)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_8(type, ptr, val) \
|
||||
{ \
|
||||
type exchange8; EA_UNUSED(exchange8); \
|
||||
EASTL_ATOMIC_EXCHANGE_SEQ_CST_8(type, exchange8, ptr, val); \
|
||||
}
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_16(type, ptr, val) \
|
||||
{ \
|
||||
type exchange16; EA_UNUSED(exchange16); \
|
||||
EASTL_ATOMIC_EXCHANGE_SEQ_CST_16(type, exchange16, ptr, val); \
|
||||
}
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_32(type, ptr, val) \
|
||||
{ \
|
||||
type exchange32; EA_UNUSED(exchange32); \
|
||||
EASTL_ATOMIC_EXCHANGE_SEQ_CST_32(type, exchange32, ptr, val); \
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* Since 64-bit exchange is wrapped around a cmpxchg8b on 32-bit x86, it is
|
||||
* faster to just do a mov; mfence.
|
||||
*/
|
||||
#if defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64(type, ptr, val) \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER(); \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_64(type, ptr, val); \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
|
||||
#elif defined(EA_PROCESSOR_X86_64)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64(type, ptr, val) \
|
||||
{ \
|
||||
type exchange64; EA_UNUSED(exchange64); \
|
||||
EASTL_ATOMIC_EXCHANGE_SEQ_CST_64(type, exchange64, ptr, val); \
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_128(type, ptr, val, SEQ_CST)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_STORE_128(type, ptr, val, MemoryOrder) \
|
||||
{ \
|
||||
type exchange128; EA_UNUSED(exchange128); \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_EXCHANGE_, MemoryOrder), _128)(type, exchange128, ptr, val); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELAXED_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_128(type, ptr, val, RELAXED)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_RELEASE_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_128(type, ptr, val, RELEASE)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_128(type, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_STORE_128(type, ptr, val, SEQ_CST)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_STORE_H */
|
||||
@@ -0,0 +1,96 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_SUB_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_SUB_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_SUB_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) - (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) - (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) - (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) - (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_SUB_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_SUB_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_SUB_FETCH_H */
|
||||
@@ -0,0 +1,42 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_THREAD_FENCE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_THREAD_FENCE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_THREAD_FENCE_*()
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_RELAXED()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQUIRE() \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_RELEASE() \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_ACQ_REL() \
|
||||
EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EA_COMPILER_MSVC) || defined(__clang__) || defined(EA_COMPILER_GNUC)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_THREAD_FENCE_SEQ_CST() \
|
||||
EASTL_ATOMIC_CPU_MB()
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_THREAD_FENCE_H */
|
||||
@@ -0,0 +1,96 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ARCH_X86_XOR_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_X86_XOR_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ARCH_ATOMIC_XOR_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EA_COMPILER_MSVC) && defined(EA_PROCESSOR_X86)
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) ^ (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) ^ (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_64_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((defined(__clang__) || defined(EA_COMPILER_GNUC)) && defined(EA_PROCESSOR_X86_64))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED(ret, observed, val) \
|
||||
ret = ((observed) ^ (val))
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET(ret, prevObserved, val) \
|
||||
ret = ((prevObserved) ^ (val))
|
||||
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELAXED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQUIRE, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, RELEASE, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, ACQ_REL, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
#define EASTL_ARCH_ATOMIC_XOR_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ARCH_ATOMIC_X86_OP_128_IMPL(type, ret, ptr, val, SEQ_CST, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_PRE_COMPUTE_DESIRED, \
|
||||
EASTL_ARCH_ATOMIC_X86_XOR_FETCH_POST_COMPUTE_RET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ARCH_X86_XOR_FETCH_H */
|
||||
@@ -0,0 +1,252 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_H
|
||||
#define EASTL_ATOMIC_INTERNAL_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#include <EASTL/internal/config.h>
|
||||
#include <EASTL/internal/move_help.h>
|
||||
#include <EASTL/internal/memory_base.h>
|
||||
#include <EASTL/type_traits.h>
|
||||
|
||||
#include "atomic_macros.h"
|
||||
#include "atomic_casts.h"
|
||||
|
||||
#include "atomic_memory_order.h"
|
||||
#include "atomic_asserts.h"
|
||||
|
||||
#include "atomic_size_aligned.h"
|
||||
#include "atomic_base_width.h"
|
||||
|
||||
#include "atomic_integral.h"
|
||||
|
||||
#include "atomic_pointer.h"
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* All of the actual implementation is done via the ATOMIC_MACROS in the compiler or arch sub folders.
|
||||
* The C++ code is merely boilerplate around these macros that actually implement the atomic operations.
|
||||
* The C++ boilerplate is also hidden behind macros.
|
||||
* This may seem more complicated but this is all meant to reduce copy-pasting and to ensure all operations
|
||||
* all end up going down to one macro that does the actual implementation.
|
||||
* The reduced code duplication makes it easier to verify the implementation and reason about it.
|
||||
* Ensures we do not have to re-implement the same code for compilers that do not support generic builtins such as MSVC.
|
||||
* Ensures for compilers that have separate intrinsics for different widths, that C++ boilerplate isn't copy-pasted leading to programmer errors.
|
||||
* Ensures if we ever have to implement a new platform, only the low-level leaf macros have to be implemented, everything else will be generated for you.
|
||||
*/
|
||||
|
||||
|
||||
#include "atomic_push_compiler_options.h"
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
template <typename T>
|
||||
struct is_atomic_lockfree_size
|
||||
{
|
||||
static EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR_OR_CONST bool value = false ||
|
||||
#if defined(EASTL_ATOMIC_HAS_8BIT)
|
||||
sizeof(T) == 1 ||
|
||||
#endif
|
||||
#if defined(EASTL_ATOMIC_HAS_16BIT)
|
||||
sizeof(T) == 2 ||
|
||||
#endif
|
||||
#if defined(EASTL_ATOMIC_HAS_32BIT)
|
||||
sizeof(T) == 4 ||
|
||||
#endif
|
||||
#if defined(EASTL_ATOMIC_HAS_64BIT)
|
||||
sizeof(T) == 8 ||
|
||||
#endif
|
||||
#if defined(EASTL_ATOMIC_HAS_128BIT)
|
||||
sizeof(T) == 16 ||
|
||||
#endif
|
||||
false;
|
||||
};
|
||||
|
||||
|
||||
template <typename T>
|
||||
struct is_user_type_suitable_for_primary_template
|
||||
{
|
||||
static EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR_OR_CONST bool value = eastl::internal::is_atomic_lockfree_size<T>::value;
|
||||
};
|
||||
|
||||
|
||||
template <typename T>
|
||||
using select_atomic_inherit_0 = typename eastl::conditional<eastl::is_same_v<bool, T> || eastl::internal::is_user_type_suitable_for_primary_template<T>::value,
|
||||
eastl::internal::atomic_base_width<T>, /* True */
|
||||
eastl::internal::atomic_invalid_type<T> /* False */
|
||||
>::type;
|
||||
|
||||
template <typename T>
|
||||
using select_atomic_inherit = select_atomic_inherit_0<T>;
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CLASS_IMPL(type, base, valueType, differenceType) \
|
||||
private: \
|
||||
\
|
||||
EASTL_ATOMIC_STATIC_ASSERT_TYPE(type); \
|
||||
\
|
||||
using Base = base; \
|
||||
\
|
||||
public: \
|
||||
\
|
||||
typedef valueType value_type; \
|
||||
typedef differenceType difference_type; \
|
||||
\
|
||||
public: \
|
||||
\
|
||||
static EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR_OR_CONST bool is_always_lock_free = eastl::internal::is_atomic_lockfree_size<type>::value; \
|
||||
\
|
||||
public: /* deleted ctors && assignment operators */ \
|
||||
\
|
||||
atomic(const atomic&) EA_NOEXCEPT = delete; \
|
||||
\
|
||||
atomic& operator=(const atomic&) EA_NOEXCEPT = delete; \
|
||||
atomic& operator=(const atomic&) volatile EA_NOEXCEPT = delete; \
|
||||
\
|
||||
public: /* ctors */ \
|
||||
\
|
||||
EA_CONSTEXPR atomic(type desired) EA_NOEXCEPT \
|
||||
: Base{ desired } \
|
||||
{ \
|
||||
} \
|
||||
\
|
||||
EA_CONSTEXPR atomic() EA_NOEXCEPT_IF(eastl::is_nothrow_default_constructible_v<type>) = default; \
|
||||
\
|
||||
public: \
|
||||
\
|
||||
bool is_lock_free() const EA_NOEXCEPT \
|
||||
{ \
|
||||
return eastl::internal::is_atomic_lockfree_size<type>::value; \
|
||||
} \
|
||||
\
|
||||
bool is_lock_free() const volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(type); \
|
||||
return false; \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_USING_ATOMIC_BASE(type) \
|
||||
public: \
|
||||
\
|
||||
using Base::operator=; \
|
||||
using Base::store; \
|
||||
using Base::load; \
|
||||
using Base::exchange; \
|
||||
using Base::compare_exchange_weak; \
|
||||
using Base::compare_exchange_strong; \
|
||||
\
|
||||
public: \
|
||||
\
|
||||
operator type() const volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
} \
|
||||
\
|
||||
operator type() const EA_NOEXCEPT \
|
||||
{ \
|
||||
return load(eastl::memory_order_seq_cst); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_USING_ATOMIC_INTEGRAL() \
|
||||
public: \
|
||||
\
|
||||
using Base::fetch_add; \
|
||||
using Base::add_fetch; \
|
||||
\
|
||||
using Base::fetch_sub; \
|
||||
using Base::sub_fetch; \
|
||||
\
|
||||
using Base::fetch_and; \
|
||||
using Base::and_fetch; \
|
||||
\
|
||||
using Base::fetch_or; \
|
||||
using Base::or_fetch; \
|
||||
\
|
||||
using Base::fetch_xor; \
|
||||
using Base::xor_fetch; \
|
||||
\
|
||||
using Base::operator++; \
|
||||
using Base::operator--; \
|
||||
using Base::operator+=; \
|
||||
using Base::operator-=; \
|
||||
using Base::operator&=; \
|
||||
using Base::operator|=; \
|
||||
using Base::operator^=;
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_USING_ATOMIC_POINTER() \
|
||||
public: \
|
||||
\
|
||||
using Base::fetch_add; \
|
||||
using Base::add_fetch; \
|
||||
using Base::fetch_sub; \
|
||||
using Base::sub_fetch; \
|
||||
\
|
||||
using Base::operator++; \
|
||||
using Base::operator--; \
|
||||
using Base::operator+=; \
|
||||
using Base::operator-=;
|
||||
|
||||
|
||||
template <typename T, typename = void>
|
||||
struct atomic : protected eastl::internal::select_atomic_inherit<T>
|
||||
{
|
||||
EASTL_ATOMIC_CLASS_IMPL(T, eastl::internal::select_atomic_inherit<T>, T, T)
|
||||
|
||||
EASTL_ATOMIC_USING_ATOMIC_BASE(T)
|
||||
};
|
||||
|
||||
|
||||
template <typename T>
|
||||
struct atomic<T, eastl::enable_if_t<eastl::is_integral_v<T> && !eastl::is_same_v<bool, T>>> : protected eastl::internal::atomic_integral_width<T>
|
||||
{
|
||||
EASTL_ATOMIC_CLASS_IMPL(T, eastl::internal::atomic_integral_width<T>, T, T)
|
||||
|
||||
EASTL_ATOMIC_USING_ATOMIC_BASE(T)
|
||||
|
||||
EASTL_ATOMIC_USING_ATOMIC_INTEGRAL()
|
||||
};
|
||||
|
||||
|
||||
template <typename T>
|
||||
struct atomic<T*> : protected eastl::internal::atomic_pointer_width<T*>
|
||||
{
|
||||
EASTL_ATOMIC_CLASS_IMPL(T*, eastl::internal::atomic_pointer_width<T*>, T*, ptrdiff_t)
|
||||
|
||||
EASTL_ATOMIC_USING_ATOMIC_BASE(T*)
|
||||
|
||||
EASTL_ATOMIC_USING_ATOMIC_POINTER()
|
||||
};
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#include "atomic_pop_compiler_options.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_H */
|
||||
@@ -0,0 +1,75 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_STATIC_ASSERTS_H
|
||||
#define EASTL_ATOMIC_INTERNAL_STATIC_ASSERTS_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(type) \
|
||||
static_assert(!eastl::is_same<type, type>::value, "eastl::atomic<T> : volatile eastl::atomic<T> is not what you expect! Read the docs in EASTL/atomic.h! Use the memory orders to access the atomic object!");
|
||||
|
||||
#define EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(type) \
|
||||
static_assert(!eastl::is_same<type, type>::value, "eastl::atomic<T> : invalid memory order for the given operation!");
|
||||
|
||||
#define EASTL_ATOMIC_STATIC_ASSERT_TYPE(type) \
|
||||
/* User Provided T must not be cv qualified */ \
|
||||
static_assert(!eastl::is_const<type>::value, "eastl::atomic<T> : Template Typename T cannot be const!"); \
|
||||
static_assert(!eastl::is_volatile<type>::value, "eastl::atomic<T> : Template Typename T cannot be volatile! Use the memory orders to access the underlying type for the guarantees you need."); \
|
||||
/* T must satisfy StandardLayoutType */ \
|
||||
static_assert(eastl::is_standard_layout<type>::value, "eastl::atomic<T> : Must have standard layout!"); \
|
||||
/* T must be TriviallyCopyable but it does not have to be TriviallyConstructible */ \
|
||||
static_assert(eastl::is_trivially_copyable<type>::value, "eastl::atomci<T> : Template Typename T must be trivially copyable!"); \
|
||||
static_assert(eastl::is_copy_constructible<type>::value, "eastl::atomic<T> : Template Typename T must be copy constructible!"); \
|
||||
static_assert(eastl::is_move_constructible<type>::value, "eastl::atomic<T> : Template Typename T must be move constructible!"); \
|
||||
static_assert(eastl::is_copy_assignable<type>::value, "eastl::atomic<T> : Template Typename T must be copy assignable!"); \
|
||||
static_assert(eastl::is_move_assignable<type>::value, "eastl::atomic<T> : Template Typename T must be move assignable!"); \
|
||||
static_assert(eastl::is_trivially_destructible<type>::value, "eastl::atomic<T> : Must be trivially destructible!"); \
|
||||
static_assert(eastl::internal::is_atomic_lockfree_size<type>::value, "eastl::atomic<T> : Template Typename T must be a lockfree size!");
|
||||
|
||||
#define EASTL_ATOMIC_STATIC_ASSERT_TYPE_IS_OBJECT(type) \
|
||||
static_assert(eastl::is_object<type>::value, "eastl::atomic<T> : Template Typename T must be an object type!");
|
||||
|
||||
#define EASTL_ATOMIC_ASSERT_ALIGNED(alignment) \
|
||||
EASTL_ASSERT((alignment & (alignment - 1)) == 0); \
|
||||
EASTL_ASSERT((reinterpret_cast<uintptr_t>(this) & (alignment - 1)) == 0)
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
template <typename T>
|
||||
struct atomic_invalid_type
|
||||
{
|
||||
/**
|
||||
* class Test { int i; int j; int k; }; sizeof(Test) == 96 bits
|
||||
*
|
||||
* std::atomic allows non-primitive types to be used for the template type.
|
||||
* This causes the api to degrade to locking for types that cannot fit into the lockfree size
|
||||
* of the target platform such as std::atomic<Test> leading to performance traps.
|
||||
*
|
||||
* If this static_assert() fired, this means your template type T is larger than any atomic instruction
|
||||
* supported on the given platform.
|
||||
*/
|
||||
|
||||
static_assert(!eastl::is_same<T, T>::value, "eastl::atomic<T> : invalid template type T!");
|
||||
};
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_STATIC_ASSERTS_H */
|
||||
@@ -0,0 +1,346 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_BASE_WIDTH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_BASE_WIDTH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#include "atomic_push_compiler_options.h"
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
template <typename T, unsigned width = sizeof(T)>
|
||||
struct atomic_base_width;
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* T does not have to be trivially default constructible but it still
|
||||
* has to be a trivially copyable type for the primary atomic template.
|
||||
* Thus we must type pun into whatever storage type of the given fixed width
|
||||
* the platform designates. This ensures T does not have to be trivially constructible.
|
||||
*/
|
||||
|
||||
#define EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits) \
|
||||
EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_FIXED_WIDTH_TYPE_, bits)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_STORE_FUNC_IMPL(op, bits) \
|
||||
EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits) fixedWidthDesired = EASTL_ATOMIC_TYPE_PUN_CAST(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), desired); \
|
||||
EA_PREPROCESSOR_JOIN(op, bits)(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), \
|
||||
EASTL_ATOMIC_TYPE_CAST(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), this->GetAtomicAddress()), \
|
||||
fixedWidthDesired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_FUNC_IMPL(op, bits) \
|
||||
EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits) retVal; \
|
||||
EA_PREPROCESSOR_JOIN(op, bits)(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), \
|
||||
retVal, \
|
||||
EASTL_ATOMIC_TYPE_CAST(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), this->GetAtomicAddress())); \
|
||||
return EASTL_ATOMIC_TYPE_PUN_CAST(T, retVal);
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_FUNC_IMPL(op, bits) \
|
||||
EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits) retVal; \
|
||||
EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits) fixedWidthDesired = EASTL_ATOMIC_TYPE_PUN_CAST(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), desired); \
|
||||
EA_PREPROCESSOR_JOIN(op, bits)(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), \
|
||||
retVal, \
|
||||
EASTL_ATOMIC_TYPE_CAST(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), this->GetAtomicAddress()), \
|
||||
fixedWidthDesired); \
|
||||
return EASTL_ATOMIC_TYPE_PUN_CAST(T, retVal);
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(op, bits) \
|
||||
EASTL_ATOMIC_DEFAULT_INIT(bool, retVal); \
|
||||
EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits) fixedWidthDesired = EASTL_ATOMIC_TYPE_PUN_CAST(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), desired); \
|
||||
EA_PREPROCESSOR_JOIN(op, bits)(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), \
|
||||
retVal, \
|
||||
EASTL_ATOMIC_TYPE_CAST(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), this->GetAtomicAddress()), \
|
||||
EASTL_ATOMIC_TYPE_CAST(EASTL_ATOMIC_BASE_FIXED_WIDTH_TYPE(bits), &expected), \
|
||||
fixedWidthDesired); \
|
||||
return retVal;
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_BASE_OP_JOIN(op, Order) \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_, op), Order)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_BASE_CMPXCHG_FUNCS_IMPL(funcName, cmpxchgOp, bits) \
|
||||
using Base::funcName; \
|
||||
\
|
||||
bool funcName(T& expected, T desired) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _SEQ_CST_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _RELAXED_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_acquire_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _ACQUIRE_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_release_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _RELEASE_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_acq_rel_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _ACQ_REL_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_seq_cst_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _SEQ_CST_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_relaxed_s, \
|
||||
eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _RELAXED_RELAXED_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_acquire_s, \
|
||||
eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _ACQUIRE_RELAXED_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_acquire_s, \
|
||||
eastl::internal::memory_order_acquire_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _ACQUIRE_ACQUIRE_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_release_s, \
|
||||
eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _RELEASE_RELAXED_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_acq_rel_s, \
|
||||
eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _ACQ_REL_RELAXED_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_acq_rel_s, \
|
||||
eastl::internal::memory_order_acquire_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _ACQ_REL_ACQUIRE_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_seq_cst_s, \
|
||||
eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _SEQ_CST_RELAXED_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_seq_cst_s, \
|
||||
eastl::internal::memory_order_acquire_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _SEQ_CST_ACQUIRE_), bits); \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& expected, T desired, \
|
||||
eastl::internal::memory_order_seq_cst_s, \
|
||||
eastl::internal::memory_order_seq_cst_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_CMPXCHG_FUNC_IMPL(EASTL_ATOMIC_BASE_OP_JOIN(cmpxchgOp, _SEQ_CST_SEQ_CST_), bits); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_BASE_CMPXCHG_WEAK_FUNCS_IMPL(bits) \
|
||||
EASTL_ATOMIC_BASE_CMPXCHG_FUNCS_IMPL(compare_exchange_weak, CMPXCHG_WEAK, bits)
|
||||
|
||||
#define EASTL_ATOMIC_BASE_CMPXCHG_STRONG_FUNCS_IMPL(bits) \
|
||||
EASTL_ATOMIC_BASE_CMPXCHG_FUNCS_IMPL(compare_exchange_strong, CMPXCHG_STRONG, bits)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_BASE_WIDTH_SPECIALIZE(bytes, bits) \
|
||||
template <typename T> \
|
||||
struct atomic_base_width<T, bytes> : public atomic_size_aligned<T> \
|
||||
{ \
|
||||
private: \
|
||||
\
|
||||
static_assert(EA_ALIGN_OF(atomic_size_aligned<T>) == bytes, "eastl::atomic<T> must be sizeof(T) aligned!"); \
|
||||
static_assert(EA_ALIGN_OF(atomic_size_aligned<T>) == sizeof(T), "eastl::atomic<T> must be sizeof(T) aligned!"); \
|
||||
using Base = atomic_size_aligned<T>; \
|
||||
\
|
||||
public: /* ctors */ \
|
||||
\
|
||||
EA_CONSTEXPR atomic_base_width(T desired) EA_NOEXCEPT \
|
||||
: Base{ desired } \
|
||||
{ \
|
||||
} \
|
||||
\
|
||||
EA_CONSTEXPR atomic_base_width() EA_NOEXCEPT_IF(eastl::is_nothrow_default_constructible_v<T>) = default; \
|
||||
\
|
||||
atomic_base_width(const atomic_base_width&) EA_NOEXCEPT = delete; \
|
||||
\
|
||||
public: /* store */ \
|
||||
\
|
||||
using Base::store; \
|
||||
\
|
||||
void store(T desired) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STORE_FUNC_IMPL(EASTL_ATOMIC_STORE_SEQ_CST_, bits); \
|
||||
} \
|
||||
\
|
||||
void store(T desired, eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STORE_FUNC_IMPL(EASTL_ATOMIC_STORE_RELAXED_, bits); \
|
||||
} \
|
||||
\
|
||||
void store(T desired, eastl::internal::memory_order_release_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STORE_FUNC_IMPL(EASTL_ATOMIC_STORE_RELEASE_, bits); \
|
||||
} \
|
||||
\
|
||||
void store(T desired, eastl::internal::memory_order_seq_cst_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STORE_FUNC_IMPL(EASTL_ATOMIC_STORE_SEQ_CST_, bits); \
|
||||
} \
|
||||
\
|
||||
public: /* load */ \
|
||||
\
|
||||
using Base::load; \
|
||||
\
|
||||
T load() const EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_LOAD_FUNC_IMPL(EASTL_ATOMIC_LOAD_SEQ_CST_, bits); \
|
||||
} \
|
||||
\
|
||||
T load(eastl::internal::memory_order_relaxed_s) const EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_LOAD_FUNC_IMPL(EASTL_ATOMIC_LOAD_RELAXED_, bits); \
|
||||
} \
|
||||
\
|
||||
T load(eastl::internal::memory_order_acquire_s) const EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_LOAD_FUNC_IMPL(EASTL_ATOMIC_LOAD_ACQUIRE_, bits); \
|
||||
} \
|
||||
\
|
||||
T load(eastl::internal::memory_order_seq_cst_s) const EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_LOAD_FUNC_IMPL(EASTL_ATOMIC_LOAD_SEQ_CST_, bits); \
|
||||
} \
|
||||
\
|
||||
public: /* exchange */ \
|
||||
\
|
||||
using Base::exchange; \
|
||||
\
|
||||
T exchange(T desired) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_EXCHANGE_FUNC_IMPL(EASTL_ATOMIC_EXCHANGE_SEQ_CST_, bits); \
|
||||
} \
|
||||
\
|
||||
T exchange(T desired, eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_EXCHANGE_FUNC_IMPL(EASTL_ATOMIC_EXCHANGE_RELAXED_, bits); \
|
||||
} \
|
||||
\
|
||||
T exchange(T desired, eastl::internal::memory_order_acquire_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_EXCHANGE_FUNC_IMPL(EASTL_ATOMIC_EXCHANGE_ACQUIRE_, bits); \
|
||||
} \
|
||||
\
|
||||
T exchange(T desired, eastl::internal::memory_order_release_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_EXCHANGE_FUNC_IMPL(EASTL_ATOMIC_EXCHANGE_RELEASE_, bits); \
|
||||
} \
|
||||
\
|
||||
T exchange(T desired, eastl::internal::memory_order_acq_rel_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_EXCHANGE_FUNC_IMPL(EASTL_ATOMIC_EXCHANGE_ACQ_REL_, bits); \
|
||||
} \
|
||||
\
|
||||
T exchange(T desired, eastl::internal::memory_order_seq_cst_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_EXCHANGE_FUNC_IMPL(EASTL_ATOMIC_EXCHANGE_SEQ_CST_, bits); \
|
||||
} \
|
||||
\
|
||||
public: /* compare_exchange_weak */ \
|
||||
\
|
||||
EASTL_ATOMIC_BASE_CMPXCHG_WEAK_FUNCS_IMPL(bits) \
|
||||
\
|
||||
public: /* compare_exchange_strong */ \
|
||||
\
|
||||
EASTL_ATOMIC_BASE_CMPXCHG_STRONG_FUNCS_IMPL(bits) \
|
||||
\
|
||||
public: /* assignment operator */ \
|
||||
\
|
||||
using Base::operator=; \
|
||||
\
|
||||
T operator=(T desired) EA_NOEXCEPT \
|
||||
{ \
|
||||
store(desired, eastl::memory_order_seq_cst); \
|
||||
return desired; \
|
||||
} \
|
||||
\
|
||||
atomic_base_width& operator=(const atomic_base_width&) EA_NOEXCEPT = delete; \
|
||||
atomic_base_width& operator=(const atomic_base_width&) volatile EA_NOEXCEPT = delete; \
|
||||
\
|
||||
};
|
||||
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_8BIT)
|
||||
EASTL_ATOMIC_BASE_WIDTH_SPECIALIZE(1, 8)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_16BIT)
|
||||
EASTL_ATOMIC_BASE_WIDTH_SPECIALIZE(2, 16)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_32BIT)
|
||||
EASTL_ATOMIC_BASE_WIDTH_SPECIALIZE(4, 32)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_64BIT)
|
||||
EASTL_ATOMIC_BASE_WIDTH_SPECIALIZE(8, 64)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_128BIT)
|
||||
EASTL_ATOMIC_BASE_WIDTH_SPECIALIZE(16, 128)
|
||||
#endif
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#include "atomic_pop_compiler_options.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_BASE_WIDTH_H */
|
||||
@@ -0,0 +1,190 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_CASTS_H
|
||||
#define EASTL_ATOMIC_INTERNAL_CASTS_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#include <EASTL/internal/type_transformations.h>
|
||||
|
||||
|
||||
#include <string.h>
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE volatile T* AtomicVolatileCast(T* ptr) EA_NOEXCEPT
|
||||
{
|
||||
static_assert(!eastl::is_volatile<volatile T*>::value, "eastl::atomic<T> : pointer must not be volatile, the pointed to type must be volatile!");
|
||||
static_assert(eastl::is_volatile<volatile T>::value, "eastl::atomic<T> : the pointed to type must be volatile!");
|
||||
|
||||
return reinterpret_cast<volatile T*>(ptr);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* Some compiler intrinsics do not operate on pointer types thus
|
||||
* doing atomic operations on pointers must be casted to the suitable
|
||||
* sized unsigned integral type.
|
||||
*
|
||||
* Some compiler intrinsics aren't generics and thus structs must also
|
||||
* be casted to the appropriate sized unsigned integral type.
|
||||
*
|
||||
* Atomic operations on an int* might have to be casted to a uint64_t on
|
||||
* a platform with 8-byte pointers as an example.
|
||||
*
|
||||
* Also doing an atomic operation on a struct, we must ensure that we observe
|
||||
* the whole struct as one atomic unit with no shearing between the members.
|
||||
* A load of a struct with two uint32_t members must be one uint64_t load,
|
||||
* not two separate uint32_t loads, thus casted to the suitable sized
|
||||
* unsigned integral type.
|
||||
*/
|
||||
template <typename Integral, typename T>
|
||||
EASTL_FORCE_INLINE volatile Integral* AtomicVolatileIntegralCast(T* ptr) EA_NOEXCEPT
|
||||
{
|
||||
static_assert(!eastl::is_volatile<volatile Integral*>::value, "eastl::atomic<T> : pointer must not be volatile, the pointed to type must be volatile!");
|
||||
static_assert(eastl::is_volatile<volatile Integral>::value, "eastl::atomic<T> : the pointed to type must be volatile!");
|
||||
static_assert(eastl::is_integral<Integral>::value, "eastl::atomic<T> : Integral cast must cast to an Integral type!");
|
||||
static_assert(sizeof(Integral) == sizeof(T), "eastl::atomic<T> : Integral and T must be same size for casting!");
|
||||
|
||||
return reinterpret_cast<volatile Integral*>(ptr);
|
||||
}
|
||||
|
||||
template <typename Integral, typename T>
|
||||
EASTL_FORCE_INLINE Integral* AtomicIntegralCast(T* ptr) EA_NOEXCEPT
|
||||
{
|
||||
static_assert(eastl::is_integral<Integral>::value, "eastl::atomic<T> : Integral cast must cast to an Integral type!");
|
||||
static_assert(sizeof(Integral) == sizeof(T), "eastl::atomic<T> : Integral and T must be same size for casting!");
|
||||
|
||||
return reinterpret_cast<Integral*>(ptr);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* These casts are meant to be used with unions or structs of larger types that must be casted
|
||||
* down to the smaller integral types. Like with 128-bit atomics and msvc intrinsics.
|
||||
*
|
||||
* struct Foo128 { __int64 array[2]; }; can be casted to a __int64*
|
||||
* since a poiter to Foo128 is a pointer to the first member.
|
||||
*/
|
||||
template <typename ToType, typename FromType>
|
||||
EASTL_FORCE_INLINE volatile ToType* AtomicVolatileTypeCast(FromType* ptr) EA_NOEXCEPT
|
||||
{
|
||||
static_assert(!eastl::is_volatile<volatile ToType*>::value, "eastl::atomic<T> : pointer must not be volatile, the pointed to type must be volatile!");
|
||||
static_assert(eastl::is_volatile<volatile ToType>::value, "eastl::atomic<T> : the pointed to type must be volatile!");
|
||||
|
||||
return reinterpret_cast<volatile ToType*>(ptr);
|
||||
}
|
||||
|
||||
template <typename ToType, typename FromType>
|
||||
EASTL_FORCE_INLINE ToType* AtomicTypeCast(FromType* ptr) EA_NOEXCEPT
|
||||
{
|
||||
return reinterpret_cast<ToType*>(ptr);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* This is a compiler guaranteed safe type punning.
|
||||
* This is useful when dealing with user defined structs.
|
||||
* struct Test { uint32_t; unint32_t; };
|
||||
*
|
||||
* Example:
|
||||
* uint64_t atomicLoad = *((volatile uint64_t*)&Test);
|
||||
* Test load = AtomicTypePunCast<Test, uint64_t>(atomicLoad);
|
||||
*
|
||||
* uint64_t comparand = AtomicTypePunCast<uint64_t, Test>(Test);
|
||||
* cmpxchg(&Test, comparand, desired);
|
||||
*
|
||||
* This can be implemented in many different ways depending on the compiler such
|
||||
* as thru a union, memcpy, reinterpret_cast<Test&>(atomicLoad), etc.
|
||||
*/
|
||||
template <typename Pun, typename T, eastl::enable_if_t<!eastl::is_same_v<Pun, T>, int> = 0>
|
||||
EASTL_FORCE_INLINE Pun AtomicTypePunCast(const T& fromType) EA_NOEXCEPT
|
||||
{
|
||||
static_assert(sizeof(Pun) == sizeof(T), "eastl::atomic<T> : Pun and T must be the same size for type punning!");
|
||||
|
||||
/**
|
||||
* aligned_storage ensures we can TypePun objects that aren't trivially default constructible
|
||||
* but still trivially copyable.
|
||||
*/
|
||||
typename eastl::aligned_storage<sizeof(Pun), alignof(Pun)>::type ret;
|
||||
memcpy(eastl::addressof(ret), eastl::addressof(fromType), sizeof(Pun));
|
||||
return reinterpret_cast<Pun&>(ret);
|
||||
}
|
||||
|
||||
template <typename Pun, typename T, eastl::enable_if_t<eastl::is_same_v<Pun, T>, int> = 0>
|
||||
EASTL_FORCE_INLINE Pun AtomicTypePunCast(const T& fromType) EA_NOEXCEPT
|
||||
{
|
||||
return fromType;
|
||||
}
|
||||
|
||||
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE T AtomicNegateOperand(T val) EA_NOEXCEPT
|
||||
{
|
||||
static_assert(eastl::is_integral<T>::value, "eastl::atomic<T> : Integral Negation must be an Integral type!");
|
||||
static_assert(!eastl::is_volatile<T>::value, "eastl::atomic<T> : T must not be volatile!");
|
||||
|
||||
return static_cast<T>(0U - static_cast<eastl::make_unsigned_t<T>>(val));
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE ptrdiff_t AtomicNegateOperand(ptrdiff_t val) EA_NOEXCEPT
|
||||
{
|
||||
return -val;
|
||||
}
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* These macros are meant to prevent inclusion hell.
|
||||
* Also so that it fits with the style of the rest of the atomic macro implementation.
|
||||
*/
|
||||
#define EASTL_ATOMIC_VOLATILE_CAST(ptr) \
|
||||
eastl::internal::AtomicVolatileCast((ptr))
|
||||
|
||||
#define EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(IntegralType, ptr) \
|
||||
eastl::internal::AtomicVolatileIntegralCast<IntegralType>((ptr))
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_CAST(IntegralType, ptr) \
|
||||
eastl::internal::AtomicIntegralCast<IntegralType>((ptr))
|
||||
|
||||
#define EASTL_ATOMIC_VOLATILE_TYPE_CAST(ToType, ptr) \
|
||||
eastl::internal::AtomicVolatileTypeCast<ToType>((ptr))
|
||||
|
||||
#define EASTL_ATOMIC_TYPE_CAST(ToType, ptr) \
|
||||
eastl::internal::AtomicTypeCast<ToType>((ptr))
|
||||
|
||||
#define EASTL_ATOMIC_TYPE_PUN_CAST(PunType, fromType) \
|
||||
eastl::internal::AtomicTypePunCast<PunType>((fromType))
|
||||
|
||||
#define EASTL_ATOMIC_NEGATE_OPERAND(val) \
|
||||
eastl::internal::AtomicNegateOperand((val))
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_CASTS_H */
|
||||
@@ -0,0 +1,170 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNA_ATOMIC_FLAG_H
|
||||
#define EASTL_ATOMIC_INTERNA_ATOMIC_FLAG_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#include "atomic_push_compiler_options.h"
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
class atomic_flag
|
||||
{
|
||||
public: /* ctors */
|
||||
|
||||
EA_CONSTEXPR atomic_flag(bool desired) EA_NOEXCEPT
|
||||
: mFlag{ desired }
|
||||
{
|
||||
}
|
||||
|
||||
EA_CONSTEXPR atomic_flag() EA_NOEXCEPT
|
||||
: mFlag{ false }
|
||||
{
|
||||
}
|
||||
|
||||
public: /* deleted ctors && assignment operators */
|
||||
|
||||
atomic_flag(const atomic_flag&) EA_NOEXCEPT = delete;
|
||||
|
||||
atomic_flag& operator=(const atomic_flag&) EA_NOEXCEPT = delete;
|
||||
atomic_flag& operator=(const atomic_flag&) volatile EA_NOEXCEPT = delete;
|
||||
|
||||
public: /* clear */
|
||||
|
||||
template <typename Order>
|
||||
void clear(Order /*order*/) volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(Order);
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
void clear(Order /*order*/) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(Order);
|
||||
}
|
||||
|
||||
void clear(eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT
|
||||
{
|
||||
mFlag.store(false, eastl::memory_order_relaxed);
|
||||
}
|
||||
|
||||
void clear(eastl::internal::memory_order_release_s) EA_NOEXCEPT
|
||||
{
|
||||
mFlag.store(false, eastl::memory_order_release);
|
||||
}
|
||||
|
||||
void clear(eastl::internal::memory_order_seq_cst_s) EA_NOEXCEPT
|
||||
{
|
||||
mFlag.store(false, eastl::memory_order_seq_cst);
|
||||
}
|
||||
|
||||
void clear() EA_NOEXCEPT
|
||||
{
|
||||
mFlag.store(false, eastl::memory_order_seq_cst);
|
||||
}
|
||||
|
||||
public: /* test_and_set */
|
||||
|
||||
template <typename Order>
|
||||
bool test_and_set(Order /*order*/) volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(Order);
|
||||
return false;
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
bool test_and_set(Order /*order*/) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(Order);
|
||||
return false;
|
||||
}
|
||||
|
||||
bool test_and_set(eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.exchange(true, eastl::memory_order_relaxed);
|
||||
}
|
||||
|
||||
bool test_and_set(eastl::internal::memory_order_acquire_s) EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.exchange(true, eastl::memory_order_acquire);
|
||||
}
|
||||
|
||||
bool test_and_set(eastl::internal::memory_order_release_s) EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.exchange(true, eastl::memory_order_release);
|
||||
}
|
||||
|
||||
bool test_and_set(eastl::internal::memory_order_acq_rel_s) EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.exchange(true, eastl::memory_order_acq_rel);
|
||||
}
|
||||
|
||||
bool test_and_set(eastl::internal::memory_order_seq_cst_s) EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.exchange(true, eastl::memory_order_seq_cst);
|
||||
}
|
||||
|
||||
bool test_and_set() EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.exchange(true, eastl::memory_order_seq_cst);
|
||||
}
|
||||
|
||||
public: /* test */
|
||||
|
||||
template <typename Order>
|
||||
bool test(Order /*order*/) const volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(Order);
|
||||
return false;
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
bool test(Order /*order*/) const EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(Order);
|
||||
return false;
|
||||
}
|
||||
|
||||
bool test(eastl::internal::memory_order_relaxed_s) const EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.load(eastl::memory_order_relaxed);
|
||||
}
|
||||
|
||||
bool test(eastl::internal::memory_order_acquire_s) const EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.load(eastl::memory_order_acquire);
|
||||
}
|
||||
|
||||
bool test(eastl::internal::memory_order_seq_cst_s) const EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.load(eastl::memory_order_seq_cst);
|
||||
}
|
||||
|
||||
bool test() const EA_NOEXCEPT
|
||||
{
|
||||
return mFlag.load(eastl::memory_order_seq_cst);
|
||||
}
|
||||
|
||||
private:
|
||||
|
||||
eastl::atomic<bool> mFlag;
|
||||
};
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#include "atomic_pop_compiler_options.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNA_ATOMIC_FLAG_H */
|
||||
@@ -0,0 +1,69 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_FLAG_STANDALONE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_FLAG_STANDALONE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// bool atomic_flag_test_and_set(eastl::atomic<T>*)
|
||||
//
|
||||
EASTL_FORCE_INLINE bool atomic_flag_test_and_set(eastl::atomic_flag* atomicObj) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->test_and_set();
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
EASTL_FORCE_INLINE bool atomic_flag_test_and_set_explicit(eastl::atomic_flag* atomicObj, Order order)
|
||||
{
|
||||
return atomicObj->test_and_set(order);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// bool atomic_flag_clear(eastl::atomic<T>*)
|
||||
//
|
||||
EASTL_FORCE_INLINE void atomic_flag_clear(eastl::atomic_flag* atomicObj)
|
||||
{
|
||||
atomicObj->clear();
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
EASTL_FORCE_INLINE void atomic_flag_clear_explicit(eastl::atomic_flag* atomicObj, Order order)
|
||||
{
|
||||
atomicObj->clear(order);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// bool atomic_flag_test(eastl::atomic<T>*)
|
||||
//
|
||||
EASTL_FORCE_INLINE bool atomic_flag_test(eastl::atomic_flag* atomicObj)
|
||||
{
|
||||
return atomicObj->test();
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
EASTL_FORCE_INLINE bool atomic_flag_test_explicit(eastl::atomic_flag* atomicObj, Order order)
|
||||
{
|
||||
return atomicObj->test(order);
|
||||
}
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_FLAG_STANDALONE_H */
|
||||
@@ -0,0 +1,344 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_INTEGRAL_H
|
||||
#define EASTL_ATOMIC_INTERNAL_INTEGRAL_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#include "atomic_push_compiler_options.h"
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(funcName) \
|
||||
template <typename Order> \
|
||||
T funcName(T /*arg*/, Order /*order*/) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(T); \
|
||||
} \
|
||||
\
|
||||
template <typename Order> \
|
||||
T funcName(T /*arg*/, Order /*order*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
} \
|
||||
\
|
||||
T funcName(T /*arg*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_INC_DEC_OPERATOR_IMPL(operatorOp) \
|
||||
T operator operatorOp() volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
} \
|
||||
\
|
||||
T operator operatorOp(int) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(operatorOp) \
|
||||
T operator operatorOp(T /*arg*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
}
|
||||
|
||||
|
||||
template <typename T, unsigned width = sizeof(T)>
|
||||
struct atomic_integral_base : public atomic_base_width<T, width>
|
||||
{
|
||||
private:
|
||||
|
||||
using Base = atomic_base_width<T, width>;
|
||||
|
||||
public: /* ctors */
|
||||
|
||||
EA_CONSTEXPR atomic_integral_base(T desired) EA_NOEXCEPT
|
||||
: Base{ desired }
|
||||
{
|
||||
}
|
||||
|
||||
EA_CONSTEXPR atomic_integral_base() EA_NOEXCEPT = default;
|
||||
|
||||
atomic_integral_base(const atomic_integral_base&) EA_NOEXCEPT = delete;
|
||||
|
||||
public: /* assignment operator */
|
||||
|
||||
using Base::operator=;
|
||||
|
||||
atomic_integral_base& operator=(const atomic_integral_base&) EA_NOEXCEPT = delete;
|
||||
atomic_integral_base& operator=(const atomic_integral_base&) volatile EA_NOEXCEPT = delete;
|
||||
|
||||
public: /* fetch_add */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(fetch_add)
|
||||
|
||||
public: /* add_fetch */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(add_fetch)
|
||||
|
||||
public: /* fetch_sub */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(fetch_sub)
|
||||
|
||||
public: /* sub_fetch */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(sub_fetch)
|
||||
|
||||
public: /* fetch_and */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(fetch_and)
|
||||
|
||||
public: /* and_fetch */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(and_fetch)
|
||||
|
||||
public: /* fetch_or */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(fetch_or)
|
||||
|
||||
public: /* or_fetch */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(or_fetch)
|
||||
|
||||
public: /* fetch_xor */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(fetch_xor)
|
||||
|
||||
public: /* xor_fetch */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_FUNCS_IMPL(xor_fetch)
|
||||
|
||||
public: /* operator++ && operator-- */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_INC_DEC_OPERATOR_IMPL(++)
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_INC_DEC_OPERATOR_IMPL(--)
|
||||
|
||||
public: /* operator+= && operator-= */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(+=)
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(-=)
|
||||
|
||||
public: /* operator&= */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(&=)
|
||||
|
||||
public: /* operator|= */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(|=)
|
||||
|
||||
public: /* operator^= */
|
||||
|
||||
EASTL_ATOMIC_INTEGRAL_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(^=)
|
||||
|
||||
};
|
||||
|
||||
|
||||
template <typename T, unsigned width = sizeof(T)>
|
||||
struct atomic_integral_width;
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_FUNC_IMPL(op, bits) \
|
||||
EASTL_ATOMIC_DEFAULT_INIT(T, retVal); \
|
||||
EA_PREPROCESSOR_JOIN(op, bits)(T, retVal, this->GetAtomicAddress(), arg); \
|
||||
return retVal;
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_FETCH_IMPL(funcName, op, bits) \
|
||||
T funcName(T arg) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_INTEGRAL_FUNC_IMPL(op, bits); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_FETCH_ORDER_IMPL(funcName, orderType, op, bits) \
|
||||
T funcName(T arg, orderType) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_INTEGRAL_FUNC_IMPL(op, bits); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_FETCH_OP_JOIN(fetchOp, Order) \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_, fetchOp), Order)
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(funcName, fetchOp, bits) \
|
||||
using Base::funcName; \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_IMPL(funcName, EASTL_ATOMIC_INTEGRAL_FETCH_OP_JOIN(fetchOp, _SEQ_CST_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_relaxed_s, \
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_OP_JOIN(fetchOp, _RELAXED_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_acquire_s, \
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_OP_JOIN(fetchOp, _ACQUIRE_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_release_s, \
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_OP_JOIN(fetchOp, _RELEASE_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_acq_rel_s, \
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_OP_JOIN(fetchOp, _ACQ_REL_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_seq_cst_s, \
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_OP_JOIN(fetchOp, _SEQ_CST_), bits)
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_FETCH_INC_DEC_OPERATOR_IMPL(operatorOp, preFuncName, postFuncName) \
|
||||
using Base::operator operatorOp; \
|
||||
\
|
||||
T operator operatorOp() EA_NOEXCEPT \
|
||||
{ \
|
||||
return preFuncName(1, eastl::memory_order_seq_cst); \
|
||||
} \
|
||||
\
|
||||
T operator operatorOp(int) EA_NOEXCEPT \
|
||||
{ \
|
||||
return postFuncName(1, eastl::memory_order_seq_cst); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_FETCH_ASSIGNMENT_OPERATOR_IMPL(operatorOp, funcName) \
|
||||
using Base::operator operatorOp; \
|
||||
\
|
||||
T operator operatorOp(T arg) EA_NOEXCEPT \
|
||||
{ \
|
||||
return funcName(arg, eastl::memory_order_seq_cst); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_INTEGRAL_WIDTH_SPECIALIZE(bytes, bits) \
|
||||
template <typename T> \
|
||||
struct atomic_integral_width<T, bytes> : public atomic_integral_base<T, bytes> \
|
||||
{ \
|
||||
private: \
|
||||
\
|
||||
using Base = atomic_integral_base<T, bytes>; \
|
||||
\
|
||||
public: /* ctors */ \
|
||||
\
|
||||
EA_CONSTEXPR atomic_integral_width(T desired) EA_NOEXCEPT \
|
||||
: Base{ desired } \
|
||||
{ \
|
||||
} \
|
||||
\
|
||||
EA_CONSTEXPR atomic_integral_width() EA_NOEXCEPT = default; \
|
||||
\
|
||||
atomic_integral_width(const atomic_integral_width&) EA_NOEXCEPT = delete; \
|
||||
\
|
||||
public: /* assignment operator */ \
|
||||
\
|
||||
using Base::operator=; \
|
||||
\
|
||||
atomic_integral_width& operator=(const atomic_integral_width&) EA_NOEXCEPT = delete; \
|
||||
atomic_integral_width& operator=(const atomic_integral_width&) volatile EA_NOEXCEPT = delete; \
|
||||
\
|
||||
public: /* fetch_add */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(fetch_add, FETCH_ADD, bits) \
|
||||
\
|
||||
public: /* add_fetch */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(add_fetch, ADD_FETCH, bits) \
|
||||
\
|
||||
public: /* fetch_sub */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(fetch_sub, FETCH_SUB, bits) \
|
||||
\
|
||||
public: /* sub_fetch */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(sub_fetch, SUB_FETCH, bits) \
|
||||
\
|
||||
public: /* fetch_and */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(fetch_and, FETCH_AND, bits) \
|
||||
\
|
||||
public: /* and_fetch */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(and_fetch, AND_FETCH, bits) \
|
||||
\
|
||||
public: /* fetch_or */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(fetch_or, FETCH_OR, bits) \
|
||||
\
|
||||
public: /* or_fetch */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(or_fetch, OR_FETCH, bits) \
|
||||
\
|
||||
public: /* fetch_xor */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(fetch_xor, FETCH_XOR, bits) \
|
||||
\
|
||||
public: /* xor_fetch */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_FUNCS_IMPL(xor_fetch, XOR_FETCH, bits) \
|
||||
\
|
||||
public: /* operator++ && operator-- */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_INC_DEC_OPERATOR_IMPL(++, add_fetch, fetch_add) \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_INC_DEC_OPERATOR_IMPL(--, sub_fetch, fetch_sub) \
|
||||
\
|
||||
public: /* operator+= && operator-= */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ASSIGNMENT_OPERATOR_IMPL(+=, add_fetch) \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ASSIGNMENT_OPERATOR_IMPL(-=, sub_fetch) \
|
||||
\
|
||||
public: /* operator&= */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ASSIGNMENT_OPERATOR_IMPL(&=, and_fetch) \
|
||||
\
|
||||
public: /* operator|= */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ASSIGNMENT_OPERATOR_IMPL(|=, or_fetch) \
|
||||
\
|
||||
public: /* operator^= */ \
|
||||
\
|
||||
EASTL_ATOMIC_INTEGRAL_FETCH_ASSIGNMENT_OPERATOR_IMPL(^=, xor_fetch) \
|
||||
\
|
||||
};
|
||||
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_8BIT)
|
||||
EASTL_ATOMIC_INTEGRAL_WIDTH_SPECIALIZE(1, 8)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_16BIT)
|
||||
EASTL_ATOMIC_INTEGRAL_WIDTH_SPECIALIZE(2, 16)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_32BIT)
|
||||
EASTL_ATOMIC_INTEGRAL_WIDTH_SPECIALIZE(4, 32)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_64BIT)
|
||||
EASTL_ATOMIC_INTEGRAL_WIDTH_SPECIALIZE(8, 64)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_128BIT)
|
||||
//JLM: fails in VS2022
|
||||
//EASTL_ATOMIC_INTEGRAL_WIDTH_SPECIALIZE(16, 128)
|
||||
#endif
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#include "atomic_pop_compiler_options.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_INTEGRAL_H */
|
||||
@@ -0,0 +1,67 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// The reason for the implementation separating out into a compiler and architecture
|
||||
// folder is as follows.
|
||||
//
|
||||
// The compiler directory is meant to implement atomics using the compiler provided
|
||||
// intrinsics. This also implies that usually the same compiler instrinsic implementation
|
||||
// can be used for any architecture the compiler supports. If a compiler provides intrinsics
|
||||
// to support barriers or atomic operations, then that implementation should be in the
|
||||
// compiler directory.
|
||||
//
|
||||
// The arch directory is meant to manually implement atomics for a specific architecture
|
||||
// such as power or x86. There may be some compiler specific code in this directory because
|
||||
// GCC inline assembly syntax may be different than another compiler as an example.
|
||||
//
|
||||
// The arch directory can also be used to implement some atomic operations ourselves
|
||||
// if we deem the compiler provided implementation to be inefficient for the given
|
||||
// architecture or we need to do some things manually for a given compiler.
|
||||
//
|
||||
// The atomic_macros directory implements the macros that the rest of the atomic
|
||||
// library uses. These macros will expand to either the compiler or arch implemented
|
||||
// macro. The arch implemented macro is given priority over the compiler implemented
|
||||
// macro if both are implemented otherwise whichever is implemented is chosen or
|
||||
// an error is emitted if none are implemented.
|
||||
//
|
||||
// The implementation being all macros has a couple nice side effects as well.
|
||||
//
|
||||
// 1. All the implementation ends up funneling into one low level macro implementation
|
||||
// which makes it easy to verify correctness, reduce copy-paste errors and differences
|
||||
// in various platform implementations.
|
||||
//
|
||||
// 2. Allows for the implementation to be implemented efficiently on compilers that do not
|
||||
// directly implement the C++ memory model in their intrinsics such as msvc.
|
||||
//
|
||||
// 3. Allows for the implementation of atomics that may not be supported on the given platform,
|
||||
// such as 128-bit atomics on 32-bit platforms since the macros will only ever be expanded
|
||||
// on platforms that support said features. This makes implementing said features pretty easy
|
||||
// since we do not have to worry about complicated feature detection in the low level implementations.
|
||||
//
|
||||
// The macro implementation may asume that all passed in types are trivially constructible thus it is
|
||||
// free to create local variables of the passed in types as it may please.
|
||||
// It may also assume that all passed in types are trivially copyable as well.
|
||||
// It cannot assume any passed in type is any given type thus is a specific type if needed, it must do an
|
||||
// EASTL_ATOMIC_TYPE_PUN_CAST() to the required type.
|
||||
//
|
||||
|
||||
|
||||
#include "compiler/compiler.h"
|
||||
#include "arch/arch.h"
|
||||
|
||||
#include "atomic_macros/atomic_macros.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_H */
|
||||
@@ -0,0 +1,156 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_ATOMIC_MACROS_H
|
||||
#define EASTL_ATOMIC_INTERNAL_ATOMIC_MACROS_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
#include <EABase/eabase.h>
|
||||
|
||||
#include "atomic_macros_base.h"
|
||||
|
||||
#include "atomic_macros_fetch_add.h"
|
||||
#include "atomic_macros_fetch_sub.h"
|
||||
|
||||
#include "atomic_macros_fetch_and.h"
|
||||
#include "atomic_macros_fetch_xor.h"
|
||||
#include "atomic_macros_fetch_or.h"
|
||||
|
||||
#include "atomic_macros_add_fetch.h"
|
||||
#include "atomic_macros_sub_fetch.h"
|
||||
|
||||
#include "atomic_macros_and_fetch.h"
|
||||
#include "atomic_macros_xor_fetch.h"
|
||||
#include "atomic_macros_or_fetch.h"
|
||||
|
||||
#include "atomic_macros_exchange.h"
|
||||
|
||||
#include "atomic_macros_cmpxchg_weak.h"
|
||||
#include "atomic_macros_cmpxchg_strong.h"
|
||||
|
||||
#include "atomic_macros_load.h"
|
||||
#include "atomic_macros_store.h"
|
||||
|
||||
#include "atomic_macros_compiler_barrier.h"
|
||||
|
||||
#include "atomic_macros_cpu_pause.h"
|
||||
|
||||
#include "atomic_macros_memory_barrier.h"
|
||||
|
||||
#include "atomic_macros_signal_fence.h"
|
||||
|
||||
#include "atomic_macros_thread_fence.h"
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_HAS_8BIT) || defined(EASTL_ARCH_ATOMIC_HAS_8BIT)
|
||||
|
||||
#define EASTL_ATOMIC_HAS_8BIT
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_HAS_16BIT) || defined(EASTL_ARCH_ATOMIC_HAS_16BIT)
|
||||
|
||||
#define EASTL_ATOMIC_HAS_16BIT
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_HAS_32BIT) || defined(EASTL_ARCH_ATOMIC_HAS_32BIT)
|
||||
|
||||
#define EASTL_ATOMIC_HAS_32BIT
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_HAS_64BIT) || defined(EASTL_ARCH_ATOMIC_HAS_64BIT)
|
||||
|
||||
#define EASTL_ATOMIC_HAS_64BIT
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_HAS_128BIT) || defined(EASTL_ARCH_ATOMIC_HAS_128BIT)
|
||||
|
||||
#define EASTL_ATOMIC_HAS_128BIT
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_8)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_8 EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_8
|
||||
|
||||
#elif defined(EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_8)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_8 EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_8
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_16)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_16 EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_16
|
||||
|
||||
#elif defined(EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_16)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_16 EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_16
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_32)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_32 EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_32
|
||||
|
||||
#elif defined(EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_32)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_32 EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_32
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_64)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_64 EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_64
|
||||
|
||||
#elif defined(EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_64)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_64 EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_64
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_128)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_128 EASTL_ARCH_ATOMIC_FIXED_WIDTH_TYPE_128
|
||||
|
||||
#elif defined(EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_128)
|
||||
|
||||
#define EASTL_ATOMIC_FIXED_WIDTH_TYPE_128 EASTL_COMPILER_ATOMIC_FIXED_WIDTH_TYPE_128
|
||||
|
||||
#endif
|
||||
|
||||
// We write some of our variables in inline assembly, which MSAN
|
||||
// doesn't understand. This macro forces initialization of those
|
||||
// variables when MSAN is enabled and doesn't pay the initialization
|
||||
// cost when it's not enabled.
|
||||
#if EA_MSAN_ENABLED
|
||||
#define EASTL_ATOMIC_DEFAULT_INIT(type, var) type var{}
|
||||
#else
|
||||
#define EASTL_ATOMIC_DEFAULT_INIT(type, var) type var
|
||||
#endif // EA_MSAN_ENABLED
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_ATOMIC_MACROS_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_ADD_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_ADD_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_ADD_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_ADD_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_ADD_FETCH_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_ADD_FETCH_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_AND_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_AND_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_AND_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_AND_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_AND_FETCH_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_AND_FETCH_H */
|
||||
@@ -0,0 +1,70 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_BASE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_BASE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_AVAILABLE(op) \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_COMPILER_, op), _AVAILABLE)
|
||||
|
||||
#define EASTL_ATOMIC_INTERNAL_ARCH_AVAILABLE(op) \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ARCH_, op), _AVAILABLE)
|
||||
|
||||
|
||||
// We can't just use static_assert(false, ...) here, since on MSVC 17.10
|
||||
// the /Zc:static_assert flag makes non-dependent static_asserts in the body of a template
|
||||
// be evaluated at template-parse time, rather than at template instantion time.
|
||||
// So instead we just make the assert dependent on the type.
|
||||
#define EASTL_ATOMIC_INTERNAL_NOT_IMPLEMENTED_ERROR(...) \
|
||||
static_assert(!eastl::is_same_v<T,T>, "eastl::atomic<T> atomic macro not implemented!")
|
||||
|
||||
|
||||
/* Compiler && Arch Not Implemented */
|
||||
#define EASTL_ATOMIC_INTERNAL_OP_PATTERN_00(op) \
|
||||
EASTL_ATOMIC_INTERNAL_NOT_IMPLEMENTED_ERROR
|
||||
|
||||
/* Arch Implemented */
|
||||
#define EASTL_ATOMIC_INTERNAL_OP_PATTERN_01(op) \
|
||||
EA_PREPROCESSOR_JOIN(EASTL_ARCH_, op)
|
||||
|
||||
/* Compiler Implmented */
|
||||
#define EASTL_ATOMIC_INTERNAL_OP_PATTERN_10(op) \
|
||||
EA_PREPROCESSOR_JOIN(EASTL_COMPILER_, op)
|
||||
|
||||
/* Compiler && Arch Implemented */
|
||||
#define EASTL_ATOMIC_INTERNAL_OP_PATTERN_11(op) \
|
||||
EA_PREPROCESSOR_JOIN(EASTL_ARCH_, op)
|
||||
|
||||
|
||||
/* This macro creates the pattern macros above for the 2x2 True-False truth table */
|
||||
#define EASTL_ATOMIC_INTERNAL_OP_HELPER1(compiler, arch, op) \
|
||||
EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_INTERNAL_OP_PATTERN_, EA_PREPROCESSOR_JOIN(compiler, arch))(op)
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// EASTL_ATOMIC_CHOOSE_OP_IMPL
|
||||
//
|
||||
// This macro chooses between the compiler or architecture implementation for a
|
||||
// given atomic operation.
|
||||
//
|
||||
// USAGE:
|
||||
//
|
||||
// EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELAXED_8)(ret, ptr, val)
|
||||
//
|
||||
#define EASTL_ATOMIC_CHOOSE_OP_IMPL(op) \
|
||||
EASTL_ATOMIC_INTERNAL_OP_HELPER1( \
|
||||
EASTL_ATOMIC_INTERNAL_COMPILER_AVAILABLE(op), \
|
||||
EASTL_ATOMIC_INTERNAL_ARCH_AVAILABLE(op), \
|
||||
op \
|
||||
)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_BASE_H */
|
||||
@@ -0,0 +1,245 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_CMPXCHG_STRONG_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_CMPXCHG_STRONG_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_CMPXCHG_STRONG_*_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_CMPXCHG_STRONG_*(bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQUIRE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_RELEASE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_RELEASE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_ACQ_REL_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_ACQ_REL_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_STRONG_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_STRONG_SEQ_CST_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_CMPXCHG_STRONG_H */
|
||||
@@ -0,0 +1,245 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_CMPXCHG_WEAK_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_CMPXCHG_WEAK_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_CMPXCHG_WEAK_*_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_CMPXCHG_WEAK_*(bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_8)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_16)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_32)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_64)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELAXED_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQUIRE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_RELEASE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_RELEASE_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_ACQ_REL_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_ACQ_REL_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_ATOMIC_CMPXCHG_WEAK_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CMPXCHG_WEAK_SEQ_CST_128)(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_CMPXCHG_WEAK_H */
|
||||
@@ -0,0 +1,30 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_COMPILER_BARRIER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_COMPILER_BARRIER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_COMPILER_BARRIER()
|
||||
//
|
||||
#define EASTL_ATOMIC_COMPILER_BARRIER() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_COMPILER_BARRIER)()
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY(const T&, type)
|
||||
//
|
||||
#define EASTL_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY(val, type) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY)(val, type)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_COMPILER_BARRIER_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_CPU_PAUSE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_CPU_PAUSE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_CPU_PAUSE()
|
||||
//
|
||||
#define EASTL_ATOMIC_CPU_PAUSE() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CPU_PAUSE)()
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_CPU_PAUSE_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_EXCHANGE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_EXCHANGE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_EXCHANGE_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_EXCHANGE_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_EXCHANGE_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_EXCHANGE_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_FETCH_ADD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_FETCH_ADD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_FETCH_ADD_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_ADD_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_ADD_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_FETCH_ADD_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_FETCH_AND_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_FETCH_AND_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_FETCH_AND_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_AND_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_AND_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_FETCH_AND_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_FETCH_OR_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_FETCH_OR_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_FETCH_OR_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_OR_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_OR_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_FETCH_OR_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_FETCH_SUB_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_FETCH_SUB_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_FETCH_SUB_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_SUB_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_SUB_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_FETCH_SUB_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_FETCH_XOR_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_FETCH_XOR_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_FETCH_XOR_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_FETCH_XOR_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_FETCH_XOR_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_FETCH_XOR_H */
|
||||
@@ -0,0 +1,75 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_LOAD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_LOAD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_LOAD_*_N(type, type ret, type * ptr)
|
||||
//
|
||||
#define EASTL_ATOMIC_LOAD_RELAXED_8(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_RELAXED_8)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_ACQUIRE_8(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_ACQUIRE_8)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_SEQ_CST_8(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_SEQ_CST_8)(type, ret, ptr)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_RELAXED_16(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_RELAXED_16)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_ACQUIRE_16(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_ACQUIRE_16)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_SEQ_CST_16(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_SEQ_CST_16)(type, ret, ptr)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_RELAXED_32(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_RELAXED_32)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_ACQUIRE_32(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_ACQUIRE_32)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_SEQ_CST_32(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_SEQ_CST_32)(type, ret, ptr)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_RELAXED_64(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_RELAXED_64)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_ACQUIRE_64(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_ACQUIRE_64)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_SEQ_CST_64(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_SEQ_CST_64)(type, ret, ptr)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_RELAXED_128(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_RELAXED_128)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_ACQUIRE_128(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_ACQUIRE_128)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_SEQ_CST_128(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_SEQ_CST_128)(type, ret, ptr)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_READ_DEPENDS_32(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_READ_DEPENDS_32)(type, ret, ptr)
|
||||
|
||||
#define EASTL_ATOMIC_LOAD_READ_DEPENDS_64(type, ret, ptr) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_LOAD_READ_DEPENDS_64)(type, ret, ptr)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_LOAD_H */
|
||||
@@ -0,0 +1,38 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_MEMORY_BARRIER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_MEMORY_BARRIER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_CPU_MB()
|
||||
//
|
||||
#define EASTL_ATOMIC_CPU_MB() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CPU_MB)()
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_CPU_WMB()
|
||||
//
|
||||
#define EASTL_ATOMIC_CPU_WMB() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CPU_WMB)()
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_CPU_RMB()
|
||||
//
|
||||
#define EASTL_ATOMIC_CPU_RMB() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_CPU_RMB)()
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_MEMORY_BARRIER_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_OR_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_OR_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_OR_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_OR_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_OR_FETCH_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_OR_FETCH_H */
|
||||
@@ -0,0 +1,34 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_SIGNAL_FENCE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_SIGNAL_FENCE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_SIGNAL_FENCE_*()
|
||||
//
|
||||
#define EASTL_ATOMIC_SIGNAL_FENCE_RELAXED() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SIGNAL_FENCE_RELAXED)()
|
||||
|
||||
#define EASTL_ATOMIC_SIGNAL_FENCE_ACQUIRE() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SIGNAL_FENCE_ACQUIRE)()
|
||||
|
||||
#define EASTL_ATOMIC_SIGNAL_FENCE_RELEASE() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SIGNAL_FENCE_RELEASE)()
|
||||
|
||||
#define EASTL_ATOMIC_SIGNAL_FENCE_ACQ_REL() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SIGNAL_FENCE_ACQ_REL)()
|
||||
|
||||
#define EASTL_ATOMIC_SIGNAL_FENCE_SEQ_CST() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SIGNAL_FENCE_SEQ_CST)()
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_SIGNAL_FENCE_H */
|
||||
@@ -0,0 +1,68 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_STORE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_STORE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_STORE_*_N(type, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_STORE_RELAXED_8(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELAXED_8)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELEASE_8(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELEASE_8)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_SEQ_CST_8(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_SEQ_CST_8)(type, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELAXED_16(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELAXED_16)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELEASE_16(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELEASE_16)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_SEQ_CST_16(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_SEQ_CST_16)(type, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELAXED_32(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELAXED_32)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELEASE_32(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELEASE_32)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_SEQ_CST_32(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_SEQ_CST_32)(type, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELAXED_64(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELAXED_64)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELEASE_64(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELEASE_64)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_SEQ_CST_64(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_SEQ_CST_64)(type, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELAXED_128(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELAXED_128)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_RELEASE_128(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_RELEASE_128)(type, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_STORE_SEQ_CST_128(type, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_STORE_SEQ_CST_128)(type, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_STORE_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_SUB_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_SUB_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_SUB_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_SUB_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_SUB_FETCH_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_SUB_FETCH_H */
|
||||
@@ -0,0 +1,34 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_THREAD_FENCE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_THREAD_FENCE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_THREAD_FENCE_*()
|
||||
//
|
||||
#define EASTL_ATOMIC_THREAD_FENCE_RELAXED() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_THREAD_FENCE_RELAXED)()
|
||||
|
||||
#define EASTL_ATOMIC_THREAD_FENCE_ACQUIRE() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_THREAD_FENCE_ACQUIRE)()
|
||||
|
||||
#define EASTL_ATOMIC_THREAD_FENCE_RELEASE() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_THREAD_FENCE_RELEASE)()
|
||||
|
||||
#define EASTL_ATOMIC_THREAD_FENCE_ACQ_REL() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_THREAD_FENCE_ACQ_REL)()
|
||||
|
||||
#define EASTL_ATOMIC_THREAD_FENCE_SEQ_CST() \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_THREAD_FENCE_SEQ_CST)()
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_THREAD_FENCE_H */
|
||||
@@ -0,0 +1,98 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MACROS_XOR_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MACROS_XOR_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_ATOMIC_XOR_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELAXED_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELAXED_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQUIRE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQUIRE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELEASE_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELEASE_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQ_REL_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQ_REL_8)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_SEQ_CST_8(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_SEQ_CST_8)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELAXED_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELAXED_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQUIRE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQUIRE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELEASE_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELEASE_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQ_REL_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQ_REL_16)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_SEQ_CST_16(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_SEQ_CST_16)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELAXED_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELAXED_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQUIRE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQUIRE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELEASE_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELEASE_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQ_REL_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQ_REL_32)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_SEQ_CST_32(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_SEQ_CST_32)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELAXED_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELAXED_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQUIRE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQUIRE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELEASE_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELEASE_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQ_REL_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQ_REL_64)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_SEQ_CST_64(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_SEQ_CST_64)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELAXED_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELAXED_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQUIRE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQUIRE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_RELEASE_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_RELEASE_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_ACQ_REL_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_ACQ_REL_128)(type, ret, ptr, val)
|
||||
|
||||
#define EASTL_ATOMIC_XOR_FETCH_SEQ_CST_128(type, ret, ptr, val) \
|
||||
EASTL_ATOMIC_CHOOSE_OP_IMPL(ATOMIC_XOR_FETCH_SEQ_CST_128)(type, ret, ptr, val)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MACROS_XOR_FETCH_H */
|
||||
@@ -0,0 +1,44 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_MEMORY_ORDER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_MEMORY_ORDER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
struct memory_order_relaxed_s {};
|
||||
struct memory_order_read_depends_s {};
|
||||
struct memory_order_acquire_s {};
|
||||
struct memory_order_release_s {};
|
||||
struct memory_order_acq_rel_s {};
|
||||
struct memory_order_seq_cst_s {};
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR auto memory_order_relaxed = internal::memory_order_relaxed_s{};
|
||||
EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR auto memory_order_read_depends = internal::memory_order_read_depends_s{};
|
||||
EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR auto memory_order_acquire = internal::memory_order_acquire_s{};
|
||||
EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR auto memory_order_release = internal::memory_order_release_s{};
|
||||
EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR auto memory_order_acq_rel = internal::memory_order_acq_rel_s{};
|
||||
EASTL_CPP17_INLINE_VARIABLE EA_CONSTEXPR auto memory_order_seq_cst = internal::memory_order_seq_cst_s{};
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_MEMORY_ORDER_H */
|
||||
@@ -0,0 +1,281 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_POINTER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_POINTER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#include "atomic_push_compiler_options.h"
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
template <typename T, unsigned width = sizeof(T)>
|
||||
struct atomic_pointer_base;
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_STATIC_ASSERT_FUNCS_IMPL(funcName) \
|
||||
template <typename Order> \
|
||||
T* funcName(ptrdiff_t /*arg*/, Order /*order*/) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(T); \
|
||||
} \
|
||||
\
|
||||
template <typename Order> \
|
||||
T* funcName(ptrdiff_t /*arg*/, Order /*order*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
} \
|
||||
\
|
||||
T* funcName(ptrdiff_t /*arg*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_STATIC_ASSERT_INC_DEC_OPERATOR_IMPL(operatorOp) \
|
||||
T* operator operatorOp() volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
} \
|
||||
\
|
||||
T* operator operatorOp(int) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(operatorOp) \
|
||||
T* operator operatorOp(ptrdiff_t /*arg*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
}
|
||||
|
||||
|
||||
template <typename T, unsigned width>
|
||||
struct atomic_pointer_base<T*, width> : public atomic_base_width<T*, width>
|
||||
{
|
||||
private:
|
||||
|
||||
using Base = atomic_base_width<T*, width>;
|
||||
|
||||
public: /* ctors */
|
||||
|
||||
EA_CONSTEXPR atomic_pointer_base(T* desired) EA_NOEXCEPT
|
||||
: Base{ desired }
|
||||
{
|
||||
}
|
||||
|
||||
EA_CONSTEXPR atomic_pointer_base() EA_NOEXCEPT = default;
|
||||
|
||||
atomic_pointer_base(const atomic_pointer_base&) EA_NOEXCEPT = delete;
|
||||
|
||||
public: /* assignment operators */
|
||||
|
||||
using Base::operator=;
|
||||
|
||||
atomic_pointer_base& operator=(const atomic_pointer_base&) EA_NOEXCEPT = delete;
|
||||
atomic_pointer_base& operator=(const atomic_pointer_base&) volatile EA_NOEXCEPT = delete;
|
||||
|
||||
public: /* fetch_add */
|
||||
|
||||
EASTL_ATOMIC_POINTER_STATIC_ASSERT_FUNCS_IMPL(fetch_add)
|
||||
|
||||
public: /* add_fetch */
|
||||
|
||||
EASTL_ATOMIC_POINTER_STATIC_ASSERT_FUNCS_IMPL(add_fetch)
|
||||
|
||||
public: /* fetch_sub */
|
||||
|
||||
EASTL_ATOMIC_POINTER_STATIC_ASSERT_FUNCS_IMPL(fetch_sub)
|
||||
|
||||
public: /* sub_fetch */
|
||||
|
||||
EASTL_ATOMIC_POINTER_STATIC_ASSERT_FUNCS_IMPL(sub_fetch)
|
||||
|
||||
public: /* operator++ && operator-- */
|
||||
|
||||
EASTL_ATOMIC_POINTER_STATIC_ASSERT_INC_DEC_OPERATOR_IMPL(++)
|
||||
|
||||
EASTL_ATOMIC_POINTER_STATIC_ASSERT_INC_DEC_OPERATOR_IMPL(--)
|
||||
|
||||
public: /* operator+= && operator-= */
|
||||
|
||||
EASTL_ATOMIC_POINTER_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(+=)
|
||||
|
||||
EASTL_ATOMIC_POINTER_STATIC_ASSERT_ASSIGNMENT_OPERATOR_IMPL(-=)
|
||||
|
||||
};
|
||||
|
||||
|
||||
template <typename T, unsigned width = sizeof(T)>
|
||||
struct atomic_pointer_width;
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_FUNC_IMPL(op, bits) \
|
||||
T* retVal; \
|
||||
{ \
|
||||
ptr_integral_type retType; \
|
||||
ptr_integral_type addend = static_cast<ptr_integral_type>(arg) * static_cast<ptr_integral_type>(sizeof(T)); \
|
||||
\
|
||||
EA_PREPROCESSOR_JOIN(op, bits)(ptr_integral_type, retType, EASTL_ATOMIC_INTEGRAL_CAST(ptr_integral_type, this->GetAtomicAddress()), addend); \
|
||||
\
|
||||
retVal = reinterpret_cast<T*>(retType); \
|
||||
} \
|
||||
return retVal;
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_FETCH_IMPL(funcName, op, bits) \
|
||||
T* funcName(ptrdiff_t arg) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_TYPE_IS_OBJECT(T); \
|
||||
EASTL_ATOMIC_POINTER_FUNC_IMPL(op, bits); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_FETCH_ORDER_IMPL(funcName, orderType, op, bits) \
|
||||
T* funcName(ptrdiff_t arg, orderType) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_TYPE_IS_OBJECT(T); \
|
||||
EASTL_ATOMIC_POINTER_FUNC_IMPL(op, bits); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_FETCH_OP_JOIN(fetchOp, Order) \
|
||||
EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_, fetchOp), Order)
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_FETCH_FUNCS_IMPL(funcName, fetchOp, bits) \
|
||||
using Base::funcName; \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_IMPL(funcName, EASTL_ATOMIC_POINTER_FETCH_OP_JOIN(fetchOp, _SEQ_CST_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_relaxed_s, \
|
||||
EASTL_ATOMIC_POINTER_FETCH_OP_JOIN(fetchOp, _RELAXED_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_acquire_s, \
|
||||
EASTL_ATOMIC_POINTER_FETCH_OP_JOIN(fetchOp, _ACQUIRE_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_release_s, \
|
||||
EASTL_ATOMIC_POINTER_FETCH_OP_JOIN(fetchOp, _RELEASE_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_acq_rel_s, \
|
||||
EASTL_ATOMIC_POINTER_FETCH_OP_JOIN(fetchOp, _ACQ_REL_), bits) \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_ORDER_IMPL(funcName, eastl::internal::memory_order_seq_cst_s, \
|
||||
EASTL_ATOMIC_POINTER_FETCH_OP_JOIN(fetchOp, _SEQ_CST_), bits)
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_FETCH_INC_DEC_OPERATOR_IMPL(operatorOp, preFuncName, postFuncName) \
|
||||
using Base::operator operatorOp; \
|
||||
\
|
||||
T* operator operatorOp() EA_NOEXCEPT \
|
||||
{ \
|
||||
return preFuncName(1, eastl::memory_order_seq_cst); \
|
||||
} \
|
||||
\
|
||||
T* operator operatorOp(int) EA_NOEXCEPT \
|
||||
{ \
|
||||
return postFuncName(1, eastl::memory_order_seq_cst); \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_FETCH_ASSIGNMENT_OPERATOR_IMPL(operatorOp, funcName) \
|
||||
using Base::operator operatorOp; \
|
||||
\
|
||||
T* operator operatorOp(ptrdiff_t arg) EA_NOEXCEPT \
|
||||
{ \
|
||||
return funcName(arg, eastl::memory_order_seq_cst); \
|
||||
}
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_POINTER_WIDTH_SPECIALIZE(bytes, bits) \
|
||||
template <typename T> \
|
||||
struct atomic_pointer_width<T*, bytes> : public atomic_pointer_base<T*, bytes> \
|
||||
{ \
|
||||
private: \
|
||||
\
|
||||
using Base = atomic_pointer_base<T*, bytes>; \
|
||||
using u_ptr_integral_type = EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(uint, bits), _t); \
|
||||
using ptr_integral_type = EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(int, bits), _t); \
|
||||
\
|
||||
public: /* ctors */ \
|
||||
\
|
||||
EA_CONSTEXPR atomic_pointer_width(T* desired) EA_NOEXCEPT \
|
||||
: Base{ desired } \
|
||||
{ \
|
||||
} \
|
||||
\
|
||||
EA_CONSTEXPR atomic_pointer_width() EA_NOEXCEPT = default; \
|
||||
\
|
||||
atomic_pointer_width(const atomic_pointer_width&) EA_NOEXCEPT = delete; \
|
||||
\
|
||||
public: /* assignment operators */ \
|
||||
\
|
||||
using Base::operator=; \
|
||||
\
|
||||
atomic_pointer_width& operator=(const atomic_pointer_width&) EA_NOEXCEPT = delete; \
|
||||
atomic_pointer_width& operator=(const atomic_pointer_width&) volatile EA_NOEXCEPT = delete; \
|
||||
\
|
||||
public: /* fetch_add */ \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_FUNCS_IMPL(fetch_add, FETCH_ADD, bits) \
|
||||
\
|
||||
public: /* add_fetch */ \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_FUNCS_IMPL(add_fetch, ADD_FETCH, bits) \
|
||||
\
|
||||
public: /* fetch_sub */ \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_FUNCS_IMPL(fetch_sub, FETCH_SUB, bits) \
|
||||
\
|
||||
public: /* sub_fetch */ \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_FUNCS_IMPL(sub_fetch, SUB_FETCH, bits) \
|
||||
\
|
||||
public: /* operator++ && operator-- */ \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_INC_DEC_OPERATOR_IMPL(++, add_fetch, fetch_add) \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_INC_DEC_OPERATOR_IMPL(--, sub_fetch, fetch_sub) \
|
||||
\
|
||||
public: /* operator+= && operator-= */ \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_ASSIGNMENT_OPERATOR_IMPL(+=, add_fetch) \
|
||||
\
|
||||
EASTL_ATOMIC_POINTER_FETCH_ASSIGNMENT_OPERATOR_IMPL(-=, sub_fetch) \
|
||||
\
|
||||
public: \
|
||||
\
|
||||
using Base::load; \
|
||||
\
|
||||
T* load(eastl::internal::memory_order_read_depends_s) EA_NOEXCEPT \
|
||||
{ \
|
||||
T* retPointer; \
|
||||
EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_LOAD_READ_DEPENDS_, bits)(T*, retPointer, this->GetAtomicAddress()); \
|
||||
return retPointer; \
|
||||
} \
|
||||
};
|
||||
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_32BIT) && EA_PLATFORM_PTR_SIZE == 4
|
||||
EASTL_ATOMIC_POINTER_WIDTH_SPECIALIZE(4, 32)
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_ATOMIC_HAS_64BIT) && EA_PLATFORM_PTR_SIZE == 8
|
||||
EASTL_ATOMIC_POINTER_WIDTH_SPECIALIZE(8, 64)
|
||||
#endif
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#include "atomic_pop_compiler_options.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_POINTER_H */
|
||||
@@ -0,0 +1,11 @@
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/* NOTE: No Header Guard */
|
||||
|
||||
|
||||
EA_RESTORE_VC_WARNING();
|
||||
|
||||
EA_RESTORE_CLANG_WARNING();
|
||||
@@ -0,0 +1,17 @@
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/* NOTE: No Header Guard */
|
||||
|
||||
|
||||
// 'class' : multiple assignment operators specified
|
||||
EA_DISABLE_VC_WARNING(4522);
|
||||
|
||||
// misaligned atomic operation may incur significant performance penalty
|
||||
// The above warning is emitted in earlier versions of clang incorrectly.
|
||||
// All eastl::atomic<T> objects are size aligned.
|
||||
// This is static and runtime asserted.
|
||||
// Thus we disable this warning.
|
||||
EA_DISABLE_CLANG_WARNING(-Watomic-alignment);
|
||||
@@ -0,0 +1,197 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_SIZE_ALIGNED_H
|
||||
#define EASTL_ATOMIC_INTERNAL_SIZE_ALIGNED_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
#include "atomic_push_compiler_options.h"
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
#define EASTL_ATOMIC_SIZE_ALIGNED_STATIC_ASSERT_CMPXCHG_IMPL(funcName) \
|
||||
template <typename OrderSuccess, typename OrderFailure> \
|
||||
bool funcName(T& /*expected*/, T /*desired*/, \
|
||||
OrderSuccess /*orderSuccess*/, \
|
||||
OrderFailure /*orderFailure*/) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(T); \
|
||||
return false; \
|
||||
} \
|
||||
\
|
||||
template <typename OrderSuccess, typename OrderFailure> \
|
||||
bool funcName(T& /*expected*/, T /*desired*/, \
|
||||
OrderSuccess /*orderSuccess*/, \
|
||||
OrderFailure /*orderFailure*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
return false; \
|
||||
} \
|
||||
\
|
||||
template <typename Order> \
|
||||
bool funcName(T& /*expected*/, T /*desired*/, \
|
||||
Order /*order*/) EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(T); \
|
||||
return false; \
|
||||
} \
|
||||
\
|
||||
template <typename Order> \
|
||||
bool funcName(T& /*expected*/, T /*desired*/, \
|
||||
Order /*order*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
return false; \
|
||||
} \
|
||||
\
|
||||
bool funcName(T& /*expected*/, T /*desired*/) volatile EA_NOEXCEPT \
|
||||
{ \
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T); \
|
||||
return false; \
|
||||
}
|
||||
|
||||
#define EASTL_ATOMIC_SIZE_ALIGNED_STATIC_ASSERT_CMPXCHG_WEAK_IMPL() \
|
||||
EASTL_ATOMIC_SIZE_ALIGNED_STATIC_ASSERT_CMPXCHG_IMPL(compare_exchange_weak)
|
||||
|
||||
#define EASTL_ATOMIC_SIZE_ALIGNED_STATIC_ASSERT_CMPXCHG_STRONG_IMPL() \
|
||||
EASTL_ATOMIC_SIZE_ALIGNED_STATIC_ASSERT_CMPXCHG_IMPL(compare_exchange_strong)
|
||||
|
||||
|
||||
template<typename T>
|
||||
struct atomic_size_aligned
|
||||
{
|
||||
public: /* ctors */
|
||||
|
||||
EA_CONSTEXPR atomic_size_aligned(T desired) EA_NOEXCEPT
|
||||
: mAtomic{ desired }
|
||||
{
|
||||
}
|
||||
|
||||
EA_CONSTEXPR atomic_size_aligned() EA_NOEXCEPT_IF(eastl::is_nothrow_default_constructible_v<T>)
|
||||
: mAtomic{} /* Value-Initialize which will Zero-Initialize Trivial Constructible types */
|
||||
{
|
||||
}
|
||||
|
||||
atomic_size_aligned(const atomic_size_aligned&) EA_NOEXCEPT = delete;
|
||||
|
||||
public: /* store */
|
||||
|
||||
template <typename Order>
|
||||
void store(T /*desired*/, Order /*order*/) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(T);
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
void store(T /*desired*/, Order /*order*/) volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T);
|
||||
}
|
||||
|
||||
void store(T /*desired*/) volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T);
|
||||
}
|
||||
|
||||
public: /* load */
|
||||
|
||||
template <typename Order>
|
||||
T load(Order /*order*/) const EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(T);
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
T load(Order /*order*/) const volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T);
|
||||
}
|
||||
|
||||
T load() const volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T);
|
||||
}
|
||||
|
||||
public: /* exchange */
|
||||
|
||||
template <typename Order>
|
||||
T exchange(T /*desired*/, Order /*order*/) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(T);
|
||||
}
|
||||
|
||||
template <typename Order>
|
||||
T exchange(T /*desired*/, Order /*order*/) volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T);
|
||||
}
|
||||
|
||||
T exchange(T /*desired*/) volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T);
|
||||
}
|
||||
|
||||
public: /* compare_exchange_weak */
|
||||
|
||||
EASTL_ATOMIC_SIZE_ALIGNED_STATIC_ASSERT_CMPXCHG_WEAK_IMPL()
|
||||
|
||||
public: /* compare_exchange_strong */
|
||||
|
||||
EASTL_ATOMIC_SIZE_ALIGNED_STATIC_ASSERT_CMPXCHG_STRONG_IMPL()
|
||||
|
||||
public: /* assignment operator */
|
||||
|
||||
T operator=(T /*desired*/) volatile EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_VOLATILE_MEM_FN(T);
|
||||
}
|
||||
|
||||
atomic_size_aligned& operator=(const atomic_size_aligned&) EA_NOEXCEPT = delete;
|
||||
atomic_size_aligned& operator=(const atomic_size_aligned&) volatile EA_NOEXCEPT = delete;
|
||||
|
||||
protected: /* Accessors */
|
||||
|
||||
T* GetAtomicAddress() const EA_NOEXCEPT
|
||||
{
|
||||
return eastl::addressof(mAtomic);
|
||||
}
|
||||
|
||||
private:
|
||||
|
||||
/**
|
||||
* Some compilers such as MSVC will align 64-bit values on 32-bit machines on
|
||||
* 4-byte boundaries which can ruin the atomicity guarantees.
|
||||
*
|
||||
* Ensure everything is size aligned.
|
||||
*
|
||||
* mutable is needed in cases such as when loads are only guaranteed to be atomic
|
||||
* using a compare exchange, such as for 128-bit atomics, so we need to be able
|
||||
* to have write access to the variable as one example.
|
||||
*/
|
||||
EA_ALIGN(sizeof(T)) mutable T mAtomic;
|
||||
};
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#include "atomic_pop_compiler_options.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_SIZE_ALIGNED_H */
|
||||
@@ -0,0 +1,470 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_STANDALONE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_STANDALONE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// bool atomic_compare_exchange_strong(eastl::atomic<T>*, T* expected, T desired)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE bool atomic_compare_exchange_strong(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type* expected,
|
||||
typename eastl::atomic<T>::value_type desired) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->compare_exchange_strong(*expected, desired);
|
||||
}
|
||||
|
||||
template <typename T, typename OrderSuccess, typename OrderFailure>
|
||||
EASTL_FORCE_INLINE bool atomic_compare_exchange_strong_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type* expected,
|
||||
typename eastl::atomic<T>::value_type desired,
|
||||
OrderSuccess orderSuccess, OrderFailure orderFailure) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->compare_exchange_strong(*expected, desired, orderSuccess, orderFailure);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// bool atomic_compare_exchange_weak(eastl::atomic<T>*, T* expected, T desired)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE bool atomic_compare_exchange_weak(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type* expected,
|
||||
typename eastl::atomic<T>::value_type desired) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->compare_exchange_weak(*expected, desired);
|
||||
}
|
||||
|
||||
template <typename T, typename OrderSuccess, typename OrderFailure>
|
||||
EASTL_FORCE_INLINE bool atomic_compare_exchange_weak_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type* expected,
|
||||
typename eastl::atomic<T>::value_type desired,
|
||||
OrderSuccess orderSuccess, OrderFailure orderFailure) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->compare_exchange_weak(*expected, desired, orderSuccess, orderFailure);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_fetch_xor(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_xor(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_xor(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_xor_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_xor(arg, order);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_xor_fetch(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_xor_fetch(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->xor_fetch(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_xor_fetch_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->xor_fetch(arg, order);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_fetch_or(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_or(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_or(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_or_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_or(arg, order);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_or_fetch(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_or_fetch(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->or_fetch(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_or_fetch_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->or_fetch(arg, order);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_fetch_and(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_and(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_and(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_and_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_and(arg, order);
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_and_fetch(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_and_fetch(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->and_fetch(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_and_fetch_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->and_fetch(arg, order);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_fetch_sub(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_sub(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::difference_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_sub(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_sub_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::difference_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_sub(arg, order);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_sub_fetch(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_sub_fetch(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::difference_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->sub_fetch(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_sub_fetch_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::difference_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->sub_fetch(arg, order);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_fetch_add(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_add(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::difference_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_add(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_fetch_add_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::difference_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->fetch_add(arg, order);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_add_fetch(eastl::atomic<T>*, T arg)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_add_fetch(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::difference_type arg) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->add_fetch(arg);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_add_fetch_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::difference_type arg,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->add_fetch(arg, order);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_exchange(eastl::atomic<T>*, T desired)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_exchange(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type desired) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->exchange(desired);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_exchange_explicit(eastl::atomic<T>* atomicObj,
|
||||
typename eastl::atomic<T>::value_type desired,
|
||||
Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->exchange(desired, order);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_load(const eastl::atomic<T>*)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_load(const eastl::atomic<T>* atomicObj) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->load();
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_load_explicit(const eastl::atomic<T>* atomicObj, Order order) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->load(order);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// T atomic_load_cond(const eastl::atomic<T>*)
|
||||
//
|
||||
template <typename T, typename Predicate>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_load_cond(const eastl::atomic<T>* atomicObj, Predicate pred) EA_NOEXCEPT
|
||||
{
|
||||
for (;;)
|
||||
{
|
||||
typename eastl::atomic<T>::value_type ret = atomicObj->load();
|
||||
|
||||
if (pred(ret))
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
EASTL_ATOMIC_CPU_PAUSE();
|
||||
}
|
||||
}
|
||||
|
||||
template <typename T, typename Predicate, typename Order>
|
||||
EASTL_FORCE_INLINE typename eastl::atomic<T>::value_type atomic_load_cond_explicit(const eastl::atomic<T>* atomicObj, Predicate pred, Order order) EA_NOEXCEPT
|
||||
{
|
||||
for (;;)
|
||||
{
|
||||
typename eastl::atomic<T>::value_type ret = atomicObj->load(order);
|
||||
|
||||
if (pred(ret))
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
EASTL_ATOMIC_CPU_PAUSE();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void atomic_store(eastl::atomic<T>*, T)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE void atomic_store(eastl::atomic<T>* atomicObj, typename eastl::atomic<T>::value_type desired) EA_NOEXCEPT
|
||||
{
|
||||
atomicObj->store(desired);
|
||||
}
|
||||
|
||||
template <typename T, typename Order>
|
||||
EASTL_FORCE_INLINE void atomic_store_explicit(eastl::atomic<T>* atomicObj, typename eastl::atomic<T>::value_type desired, Order order) EA_NOEXCEPT
|
||||
{
|
||||
atomicObj->store(desired, order);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void eastl::atomic_thread_fence(Order)
|
||||
//
|
||||
template <typename Order>
|
||||
EASTL_FORCE_INLINE void atomic_thread_fence(Order) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(Order);
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_thread_fence(eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_THREAD_FENCE_RELAXED();
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_thread_fence(eastl::internal::memory_order_acquire_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_THREAD_FENCE_ACQUIRE();
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_thread_fence(eastl::internal::memory_order_release_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_THREAD_FENCE_RELEASE();
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_thread_fence(eastl::internal::memory_order_acq_rel_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_THREAD_FENCE_ACQ_REL();
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_thread_fence(eastl::internal::memory_order_seq_cst_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_THREAD_FENCE_SEQ_CST();
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void eastl::atomic_signal_fence(Order)
|
||||
//
|
||||
template <typename Order>
|
||||
EASTL_FORCE_INLINE void atomic_signal_fence(Order) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_STATIC_ASSERT_INVALID_MEMORY_ORDER(Order);
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_signal_fence(eastl::internal::memory_order_relaxed_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_SIGNAL_FENCE_RELAXED();
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_signal_fence(eastl::internal::memory_order_acquire_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_SIGNAL_FENCE_ACQUIRE();
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_signal_fence(eastl::internal::memory_order_release_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_SIGNAL_FENCE_RELEASE();
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_signal_fence(eastl::internal::memory_order_acq_rel_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_SIGNAL_FENCE_ACQ_REL();
|
||||
}
|
||||
|
||||
EASTL_FORCE_INLINE void atomic_signal_fence(eastl::internal::memory_order_seq_cst_s) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_SIGNAL_FENCE_SEQ_CST();
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void eastl::compiler_barrier()
|
||||
//
|
||||
EASTL_FORCE_INLINE void compiler_barrier() EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_COMPILER_BARRIER();
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void eastl::compiler_barrier_data_dependency(const T&)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE void compiler_barrier_data_dependency(const T& val) EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY(val, T);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void eastl::cpu_pause()
|
||||
//
|
||||
EASTL_FORCE_INLINE void cpu_pause() EA_NOEXCEPT
|
||||
{
|
||||
EASTL_ATOMIC_CPU_PAUSE();
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// bool eastl::atomic_is_lock_free(eastl::atomic<T>*)
|
||||
//
|
||||
template <typename T>
|
||||
EASTL_FORCE_INLINE bool atomic_is_lock_free(const eastl::atomic<T>* atomicObj) EA_NOEXCEPT
|
||||
{
|
||||
return atomicObj->is_lock_free();
|
||||
}
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_STANDALONE_H */
|
||||
@@ -0,0 +1,120 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Include the compiler specific implementations
|
||||
//
|
||||
#if defined(EA_COMPILER_GNUC) || defined(__clang__)
|
||||
|
||||
#include "gcc/compiler_gcc.h"
|
||||
|
||||
#elif defined(EA_COMPILER_MSVC)
|
||||
|
||||
#include "msvc/compiler_msvc.h"
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
namespace eastl
|
||||
{
|
||||
|
||||
|
||||
namespace internal
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* This can be used by specific compiler implementations to implement a data dependency compiler barrier.
|
||||
* Some compiler barriers do not take in input dependencies as is possible with the gcc asm syntax.
|
||||
* Thus we need a way to create a false dependency on the input variable so the compiler does not dead-store
|
||||
* remove it.
|
||||
* A volatile function pointer ensures the compiler must always load the function pointer and call thru it
|
||||
* since the compiler cannot reason about any side effects. Thus the compiler must always assume the
|
||||
* input variable may be accessed and thus cannot be dead-stored. This technique works even in the presence
|
||||
* of Link-Time Optimization. A compiler barrier with a data dependency is useful in these situations.
|
||||
*
|
||||
* void foo()
|
||||
* {
|
||||
* eastl::vector<int> v;
|
||||
* while (Benchmark.ContinueRunning())
|
||||
* {
|
||||
* v.push_back(0);
|
||||
* eastl::compiler_barrier(); OR eastl::compiler_barrier_data_dependency(v);
|
||||
* }
|
||||
* }
|
||||
*
|
||||
* We are trying to benchmark the push_back function of a vector. The vector v has only local scope.
|
||||
* The compiler is well within its writes to remove all accesses to v even with the compiler barrier
|
||||
* because there are no observable uses of the vector v.
|
||||
* The compiler barrier data dependency ensures there is an input dependency on the variable so that
|
||||
* it isn't removed. This is also useful when writing test code that the compiler may remove.
|
||||
*/
|
||||
|
||||
typedef void (*CompilerBarrierDataDependencyFuncPtr)(void*);
|
||||
|
||||
extern EASTL_API volatile CompilerBarrierDataDependencyFuncPtr gCompilerBarrierDataDependencyFunc;
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY_FUNC(ptr) \
|
||||
eastl::internal::gCompilerBarrierDataDependencyFunc(ptr)
|
||||
|
||||
|
||||
} // namespace internal
|
||||
|
||||
|
||||
} // namespace eastl
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#include "compiler_fetch_add.h"
|
||||
#include "compiler_fetch_sub.h"
|
||||
|
||||
#include "compiler_fetch_and.h"
|
||||
#include "compiler_fetch_xor.h"
|
||||
#include "compiler_fetch_or.h"
|
||||
|
||||
#include "compiler_add_fetch.h"
|
||||
#include "compiler_sub_fetch.h"
|
||||
|
||||
#include "compiler_and_fetch.h"
|
||||
#include "compiler_xor_fetch.h"
|
||||
#include "compiler_or_fetch.h"
|
||||
|
||||
#include "compiler_exchange.h"
|
||||
|
||||
#include "compiler_cmpxchg_weak.h"
|
||||
#include "compiler_cmpxchg_strong.h"
|
||||
|
||||
#include "compiler_load.h"
|
||||
#include "compiler_store.h"
|
||||
|
||||
#include "compiler_barrier.h"
|
||||
|
||||
#include "compiler_cpu_pause.h"
|
||||
|
||||
#include "compiler_memory_barrier.h"
|
||||
|
||||
#include "compiler_signal_fence.h"
|
||||
|
||||
#include "compiler_thread_fence.h"
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_ADD_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_ADD_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_ADD_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_ADD_FETCH_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_ADD_FETCH_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_AND_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_AND_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_AND_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_AND_FETCH_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_AND_FETCH_H */
|
||||
@@ -0,0 +1,36 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_BARRIER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_BARRIER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_COMPILER_BARRIER()
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_COMPILER_BARRIER)
|
||||
#define EASTL_COMPILER_ATOMIC_COMPILER_BARRIER_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_COMPILER_BARRIER_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY(const T&, type)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY)
|
||||
#define EASTL_COMPILER_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_COMPILER_BARRIER_DATA_DEPENDENCY_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_BARRIER_H */
|
||||
@@ -0,0 +1,430 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_CMPXCHG_STRONG_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_CMPXCHG_STRONG_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_*_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_8(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_16(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_32(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_64(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELAXED_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_RELEASE_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_STRONG_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_CMPXCHG_STRONG_H */
|
||||
@@ -0,0 +1,430 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_CMPXCHG_WEAK_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_CMPXCHG_WEAK_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_*_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_*_N(type, bool ret, type * ptr, type * expected, type desired)
|
||||
//
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_8(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_8_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_8(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_8(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_16(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_16_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_16(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_16(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_32(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_32_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_32(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_32(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_64(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_64_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_64(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_64(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELAXED_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQUIRE_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_RELEASE_RELAXED_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_ACQ_REL_ACQUIRE_128(type, ret, ptr, expected, desired)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_128_AVAILABLE \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128_AVAILABLE
|
||||
#define EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_128(type, ret, ptr, expected, desired) \
|
||||
EASTL_COMPILER_ATOMIC_CMPXCHG_WEAK_SEQ_CST_SEQ_CST_128(type, ret, ptr, expected, desired)
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_CMPXCHG_WEAK_H */
|
||||
@@ -0,0 +1,32 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_CPU_PAUSE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_CPU_PAUSE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_CPU_PAUSE()
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CPU_PAUSE)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_PAUSE_AVAILABLE 1
|
||||
|
||||
#else
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_PAUSE() \
|
||||
((void)0)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_PAUSE_AVAILABLE 1
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_CPU_PAUSE_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_EXCHANGE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_EXCHANGE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_EXCHANGE_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_EXCHANGE_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_EXCHANGE_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_ADD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_ADD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_FETCH_ADD_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_ADD_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_ADD_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_AND_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_AND_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_FETCH_AND_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_AND_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_AND_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_OR_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_OR_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_FETCH_OR_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_OR_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_OR_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_SUB_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_SUB_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_FETCH_SUB_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_SUB_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_SUB_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_XOR_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_XOR_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_FETCH_XOR_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_FETCH_XOR_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_FETCH_XOR_H */
|
||||
@@ -0,0 +1,139 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_LOAD_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_LOAD_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_LOAD_*_N(type, type ret, type * ptr)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* NOTE:
|
||||
*
|
||||
* These are used for data-dependent reads thru a pointer. It is safe
|
||||
* to assume that pointer-sized reads are atomic on any given platform.
|
||||
* This implementation assumes the hardware doesn't reorder dependent
|
||||
* loads unlike the DEC Alpha.
|
||||
*/
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_READ_DEPENDS_N(type, ret, ptr) \
|
||||
{ \
|
||||
static_assert(eastl::is_pointer_v<type>, "eastl::atomic<T> : Read Depends Type must be a Pointer Type!"); \
|
||||
static_assert(eastl::is_pointer_v<eastl::remove_pointer_t<decltype(ptr)>>, "eastl::atomic<T> : Read Depends Ptr must be a Pointer to a Pointer!"); \
|
||||
\
|
||||
ret = (*EASTL_ATOMIC_VOLATILE_CAST(ptr)); \
|
||||
}
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_READ_DEPENDS_32(type, ret, ptr) \
|
||||
EASTL_COMPILER_ATOMIC_LOAD_READ_DEPENDS_N(type, ret, ptr)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_READ_DEPENDS_64(type, ret, ptr) \
|
||||
EASTL_COMPILER_ATOMIC_LOAD_READ_DEPENDS_N(type, ret, ptr)
|
||||
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_READ_DEPENDS_32_AVAILABLE 1
|
||||
#define EASTL_COMPILER_ATOMIC_LOAD_READ_DEPENDS_64_AVAILABLE 1
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_LOAD_H */
|
||||
@@ -0,0 +1,47 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_MEMORY_BARRIER_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_MEMORY_BARRIER_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_CPU_MB()
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CPU_MB)
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_MB_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_MB_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_CPU_WMB()
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CPU_WMB)
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_WMB_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_WMB_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_CPU_RMB()
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_CPU_RMB)
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_RMB_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_CPU_RMB_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_MEMORY_BARRIER_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_OR_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_OR_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_OR_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_OR_FETCH_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_OR_FETCH_H */
|
||||
@@ -0,0 +1,49 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_SIGNAL_FENCE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_SIGNAL_FENCE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_*()
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_RELAXED)
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_RELAXED_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_RELAXED_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_ACQUIRE)
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_ACQUIRE_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_ACQUIRE_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_RELEASE)
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_RELEASE_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_RELEASE_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_ACQ_REL)
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_ACQ_REL_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_ACQ_REL_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_SEQ_CST)
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_SEQ_CST_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SIGNAL_FENCE_SEQ_CST_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_SIGNAL_FENCE_H */
|
||||
@@ -0,0 +1,113 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_STORE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_STORE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_STORE_*_N(type, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_STORE_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_STORE_H */
|
||||
@@ -0,0 +1,173 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_SUB_FETCH_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_SUB_FETCH_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_SUB_FETCH_*_N(type, type ret, type * ptr, type val)
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_8)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_8)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_8)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_8)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_8_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_8_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_16)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_16)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_16)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_16)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_16_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_16_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_32)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_32)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_32)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_32)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_32_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_32_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_64)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_64)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_64)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_64)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_64_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_64_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_128)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELAXED_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQUIRE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_128)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_RELEASE_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_128)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_ACQ_REL_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_128)
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_128_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_SUB_FETCH_SEQ_CST_128_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_SUB_FETCH_H */
|
||||
@@ -0,0 +1,49 @@
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) Electronic Arts Inc. All rights reserved.
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
#ifndef EASTL_ATOMIC_INTERNAL_COMPILER_THREAD_FENCE_H
|
||||
#define EASTL_ATOMIC_INTERNAL_COMPILER_THREAD_FENCE_H
|
||||
|
||||
#if defined(EA_PRAGMA_ONCE_SUPPORTED)
|
||||
#pragma once
|
||||
#endif
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// void EASTL_COMPILER_ATOMIC_THREAD_FENCE_*()
|
||||
//
|
||||
#if defined(EASTL_COMPILER_ATOMIC_THREAD_FENCE_RELAXED)
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_RELAXED_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_RELAXED_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_THREAD_FENCE_ACQUIRE)
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_ACQUIRE_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_ACQUIRE_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_THREAD_FENCE_RELEASE)
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_RELEASE_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_RELEASE_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_THREAD_FENCE_ACQ_REL)
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_ACQ_REL_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_ACQ_REL_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
#if defined(EASTL_COMPILER_ATOMIC_THREAD_FENCE_SEQ_CST)
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_SEQ_CST_AVAILABLE 1
|
||||
#else
|
||||
#define EASTL_COMPILER_ATOMIC_THREAD_FENCE_SEQ_CST_AVAILABLE 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* EASTL_ATOMIC_INTERNAL_COMPILER_THREAD_FENCE_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user